Atmel XMEGA B, User Manual

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91 XMEGA B [DATASHEET]
8291B–AVR–01/2013
Table 7-8. External oscillator selection and start-up time.
Notes: 1. This option should be used only when frequency stability at startup is not important for the application. The option is not suitable for crystals.
2. This option is intended for use with ceramic resonators. It can also be used when the frequency stability at startup is not important for the
application.
3. When the external oscillator is used as the reference for a DFLL, only EXTCLK and 32KHZ can be selected.
4. When the 0.4 - 16 MHz crystal oscillators selected, the MSB is then XOSCPWR.
7.10.4 XOSCFAIL – XOSC Failure Detection register

Bit 7:4 – Reserved
These bits are reserved and will always be read as zero. For compatibility with future devices, always write these bits to
zero when this register is written.

Bit 3 – PLLFDIF: PLL Fault Detection Flag
If PLL failure detection is enabled, PLLFDIF is set when the PLL looses lock. Writing logic one to this location will clear
PLLFDIF.

Bit 2 – PLLFDEN: PLL Fault Detection Enable
Setting this bit will enable PLL failure detection. A non-maskable interrupt will be issued when PLLFDIF is set.
This bit is protected by the configuration change protection mechanism. Refer to “Configuration Change Protection” on
page 14 for details.

Bit 1 – XOSCFDIF: Failure Detection Interrupt Flag
If the external clock source oscillator failure monitor is enabled, XOSCFDIF is set when a failure is detected. Writing logic
one to this location will clear XOSCFDIF.
 Bit 0 – XOSCFDEN: Failure Detection Enable
Setting this bit will enable the failure detection monitor, and a non-maskable interrupt will be issued when XOSCFDIF is
set.
This bit is protected by the configuration change protection mechanism. Refer to “Configuration Change Protection” on
page 14 for details. Once enabled, failure detection can only be disabled by a reset.
XOSCSEL[4:0] Group configuration Selected clock source Start-up time
00000 EXTCLK
(3)
External Clock from XTAL1 pin 6 CLK
nnn
01 EXTCLK_Cn
(3)
External Clock from Port C pin n 6 CLK
00010 32KHZ
(3)
32.768kHz TOSC 16K CLK
x
(4)
0011 XTAL_256CLK
(1)
0.4MHz - 16MHz XTAL 256 CLK
x
(4)
0111 XTAL_1KCLK
(2)
0.4MHz - 16MHz XTAL 1K CLK
x
(4)
1011 XTAL_16KCLK 0.4MHz - 16MHz XTAL 16K CLK
Bit 7 6 5 4 3 2 1 0
+0x03
– – – – PLLFDIF PLLFDEN XOSCFDIF XOSCFDEN
Read/Write R R R R R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0