Atmel XMEGA B, User Manual

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359 XMEGA B [DATASHEET]
8291B–AVR–01/2013
28. IEEE 1149.1 JTAG Boundary Scan Interface
28.1 Features
•
JTAG (IEEE Std. 1149.1-2001 compliant) interface
•
Boundary scan capabilities according to the JTAG standard
•
Full scan of all I/O pins
•
Supports the mandatory SAMPLE, IDCODE, PRELOAD, EXTEST, and BYPASS instructions
•
Supports the optional HIGHZ and CLAMP instructions
•
Supports the AVR-specific PDICOM instruction for accessing the PDI
28.2 Overview
The JTAG interface is mainly intended for testing PCBs by using the JTAG boundary scan capability. Secondarily, the
JTAG interface is used to access the Program and Debug Interface (PDI) in its optional JTAG mode.
The boundary scan chain has the capability of driving and observing the logic levels on I/O pins. At the system level, all
microcontroller or board components having JTAG capabilities are connected serially by the TDI/TDO signals to form a
long shift register. An external controller sets up the devices to drive values at their output pins, and observes the input
values received from other devices. The controller compares the received data with the expected result. In this way,
boundary scan method provides a mechanism for testing the interconnections and integrity of components on printed
circuit boards by using only the four test access port (TAP) signals.
The IEEE Std. 1149.1-2001 defined mandatory JTAG instructions, IDCODE, BYPASS, SAMPLE/ PRELOAD, and
EXTEST, together with the optional CLAMP and HIGHZ instructions can be used for testing the printed circuit board.
Alternatively, the HIGHZ instruction can be used to place all I/O pins in an inactive drive state, while bypassing the
boundary scan register chain of the chip.
The AVR-specific PDICOM instruction makes it possible to use the PDI data register as an interface for accessing the
PDI for programming and debugging. This provides an alternative way to access internal programming and debugging
resources by using the JTAG interface. For more details on PDI, programming, and on-chip debugging, refer to
“Program
and Debug Interface” on page 408 .
The JTAGEN fuse must be programmed and the JTAGD bit in the MCUCR register must be cleared to enable the JTAG
interface and TAP. See
“FUSEBYTE4 – Fuse Byte4” on page 33 , and “MCUCR – Control register” on page 48 for more
details.
When using the JTAG interface for boundary scan, the JTAG TCK clock frequency can be higher than the internal device
frequency. A system clock in the device is not required for boundary scan.
28.3 TAP - Test Access Port
The JTAG interface requires and uses four device I/O pins. In JTAG terminology, these pins constitute the test access
port,or TAP. These pins are:

TMS: Test mode select. The pin is used for navigating through the TAP-controller state machine

TCK: Test clock. This is the JTAG clock signal, and all operation is synchronous to TCK

TDI: Test data in. Serial input data to be shifted in to the instruction register or data register (scan chains)

TDO: Test data out. Serial output data from the instruction register or data register
The IEEE Std. 1149.1-2001 also specifies an optional test reset signal, TRST. This signal is not available.
When the JTAGEN fuse is unprogrammed or the JTAG disable bit is set, the JTAG interface is disabled. The four TAP
pins are normal port pins, and the TAP controller is in reset. When enabled, the input TAP signals are internally pulled
high and JTAG is enabled for boundary scan operations.