Atmel XMEGA B, User Manual

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276 XMEGA B [DATASHEET]
8291B–AVR–01/2013
21.10 USART in Master SPI Mode
Using the USART in master SPI mode requires the transmitter to be enabled. The receiver can optionally be enabled to
serve as the serial input. The XCK pin will be used as the transfer clock.
As for the USART, a data transfer is initiated by writing to the DATA register. This is the case for both sending and
receiving data, since the transmitter controls the transfer clock. The data written to DATA are moved from the transmit
buffer to the shift register when the shift register is ready to send a new frame.
The transmitter and receiver interrupt flags and corresponding USART interrupts used in master SPI mode are identical
in function to their use in normal USART operation. The receiver error status flags are not in use and are always read as
zero.
Disabling of the USART transmitter or receiver in master SPI mode is identical to their disabling in normal USART
operation.
21.11 USART SPI vs. SPI
The USART in master SPI mode is fully compatible with the standalone SPI module in that:

Timing diagrams are the same

UCPHA bit functionality is identical to that of the SPI CPHA bit

UDORD bit functionality is identical to that of the SPI DORD bit
When the USART is set in master SPI mode, configuration and use are in some cases different from those of the
standalone SPI module. In addition, the following differences exist:
921.6k
19 -4 -0.8 27 -3 -0.8
75 -6 -0.1 107 -5 -0.1
1.382M
7 -4 0.6 15 -3 0.6
57 -7 0.1 121 -6 0.1
1.843M
3 -5 -0.8 19 -4 -0.8
11 -7 -0.1 75 -6 -0.1
2.00M 0 0 0.0 1 0 0.0
2.304M – – –
3 -2 -0.8
47 -6 -0.1
2.5M – – –
19 -4 0.4
77 -7 -0.1
3.0M – – –
11 -5 -0.8
43 -7 -0.2
4.0M – – – 0 0 0.0
Max 2.0Mbps 4.0Mbps
Baud f
OSC
= 32.0000MHz
rate
(bps)
CLK2X = 0 CLK2X = 1
BSEL BSCALE Error [%] BSEL BSCALE Error [%]