Atmel XMEGA B, User Manual

Page: 9 / 415

9 XMEGA B [DATASHEET]
8291B–AVR–01/2013
3.5 Program Flow
After reset, the CPU starts to execute instructions from the lowest address in the flash program memory ‘0.’ The program
counter (PC) addresses the next instruction to be fetched.
Program flow is provided by conditional and unconditional jump and call instructions capable of addressing the whole
address space directly. Most AVR instructions use a 16-bit word format, while a limited number use a 32-bit format.
During interrupts and subroutine calls, the return address PC is stored on the stack. The stack is allocated in the general
data SRAM, and consequently the stack size is only limited by the total SRAM size and the usage of the SRAM. After
reset, the stack pointer (SP) points to the highest address in the internal SRAM. The SP is read/write accessible in the
I/O memory space, enabling easy implementation of multiple stacks or stack areas. The data SRAM can easily be
accessed through the five different addressing modes supported in the AVR CPU.
3.6 Instruction Execution Timing
The AVR CPU is clocked by the CPU clock, clk
CPU
. No internal clock division is used. Figure 3-2 on page 9 shows the
parallel instruction fetches and instruction executions enabled by the Harvard architecture and the fast-access register
file concept. This is the basic pipelining concept used to obtain up to 1MIPS/MHz performance with high power efficiency.
Figure 3-2. The parallel instruction fetches and instruction executions.
Figure 3-3 on page 9 shows the internal timing concept for the register file. In a single clock cycle, an ALU operation
using two register operands is executed and the result is stored back to the destination register.
Figure 3-3. Single Cycle ALU Operation
clk
1st Instruction Fetch
1st Instruction Execute
2nd Instruction Fetch
2nd Instruction Execute
3rd Instruction Fetch
3rd Instruction Execute
4th Instruction Fetch
T1 T2 T3 T4
CPU
Total Execution Time
Register Operands Fetch
ALU Operation Execute
Result Write Back
T1 T2 T3 T4
clk
CPU