Atmel XMEGA B, User Manual

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249 XMEGA B [DATASHEET]
8291B–AVR–01/2013
Table 19-5. CMD bit description.
Writing a command to the CMD bits will clear the master interrupt flags and the CLKHOLD flag.
19.9.4 STATUS – Status register
 Bit 7
–
RIF: Read Interrupt Flag
This flag is set when a byte is successfully received in master read mode; i.e., no arbitration was lost or bus error
occurred during the operation. Writing a one to this bit location will clear RIF. When this flag is set, the master forces the
SCL line low, stretching the TWI clock period. Clearing the interrupt flags will release the SCL line.
This flag is also cleared automatically when:

Writing to the ADDR register

Writing to the DATA register

Reading the DATA register

Writing a valid command to the CMD bits in the CTRLC register

Bit 6
–
WIF: Write Interrupt Flag
This flagis set when a byte is transmitted in master write mode. The flag is set regardless of the occurrence of a bus error
or an arbitration lost condition. WIF is also set if arbitration is lost during sending of a NACK in master read mode, and if
issuing a START condition when the bus state is unknown. Writing a one to this bit location will clear WIF. When this flag
is set, the master forces the SCL line low, stretching the TWI clock period. Clearing the interrupt flags will release the
SCL line.
The flag is also cleared automatically for the same conditions as RIF.
 Bit 5
–
CLKHOLD: Clock Hold
This flag is set when the master is holding the SCL line low. This is a status flag and a read-only flag that is set when RIF
or WIF is set. Clearing the interrupt flags and releasing the SCL line will indirectly clear this flag.
The flag is also cleared automatically for the same conditions as RIF.
CMD[1:0] Group Configuration MODE Operation
00 NOACT X Reserved
01 START X
Execute acknowledge action succeeded by
repeated START condition
10 BYTEREC
W No operation
R
Execute acknowledge action succeeded by a byte
receive
11 STOP X
Execute acknowledge action succeeded by issuing
a STOP condition
Bit 7 6 5 4 3 2 1 0
+0x03
RIF WIF CLKHOLD RXACK ARBLOST BUSERR BUSSTATE[1:0]
Read/Write R/W R/W R R R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0