Atmel XMEGA B, User Manual

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268 XMEGA B [DATASHEET]
8291B–AVR–01/2013
Figure 21-3. Synchronous mode XCK timing.
Using the inverted I/O (INVEN) setting for the corresponding XCK port pin, the XCK clock edges used for data sampling
and data change can be selected. If inverted I/O is disabled (INVEN=0), data will be changed at the rising XCK clock
edge and sampled at the falling XCK clock edge. If inverted I/O is enabled (INVEN=1), data will be changed at the falling
XCK clock edge and sampled at the rising XCK clock edge. For more details, see
“I/O Ports” on page 126 .
21.3.5 Master SPI Mode Clock Generation
For master SPI mode operation, only internal clock generation is supported. This is identical to the USART synchronous
master mode, and the baud rate or BSEL setting is calculated using the same equations (see
Table 21-1 on page 266 ).
There are four combinations of the SPI clock (SCK) phase and polarity with respect to the serial data, and these are
determined by the clock phase (UCPHA) control bit and the inverted I/O pin (INVEN) settings. The data transfer timing
diagrams are shown in
Figure 21-4 on page 269 . Data bits are shifted out and latched in on opposite edges of the XCK
signal, ensuring sufficient time for data signals to stabilize. The UCPHA and INVEN settings are summarized in Table 21-
2 . Changing the setting of any of these bits during transmission will corrupt both the receiver and transmitter
Table 21-2. INVEN and UCPHA functionality.
The leading edge is the first clock edge of a clock cycle. The trailing edge is the last clock edge of a clock cycle.
RxD / TxD
XCK
RxD / TxD
XCK UCPOL = 0
UCPOL = 1
Sample
Sample
SPI Mode INVEN UCPHA Leading Edge Trailing Edge
0 0 0 Rising, sample Falling, setup
1 0 1 Rising, setup Falling, sample
2 1 0 Falling, sample Rising, setup
3 1 1 Falling, setup Rising, sample