Atmel XMEGA B, User Manual

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332 XMEGA B [DATASHEET]
8291B–AVR–01/2013
Figure 26-12.ADC prescaler.
The propagation delay of an ADC measurement is given by:
RESOLUTION is the resolution, 8 or 12 bits. The propagation delay will increase by extra ADC clock cycles if the gain
stage (GAIN) is used. A new ADC conversion can start as soon as the previous is completed.
The most-significant bit (msb) of the result is converted first, and the rest of the bits are converted during the next three
(for 8-bit results) or five (for 12-bit results) ADC clock cycles. Converting one bit takes a half ADC clock period. During the
last cycle, the result is prepared before the interrupt flag is set and the result is available in the result register for readout.
26.9.1 Single Conversion without Gain
Figure 26-13 on page 332 shows the ADC timing for a single conversion without gain. The writing of the start conversion
bit, or the event triggering the conversion (START), must occur at least one peripheral clock cycle before the ADC clock
cycle on which the conversion starts (indicated with the grey slope of the START trigger).
The input source is sampled in the first half of the first cycle.
Figure 26-13.ADC timing for one single conversion without gain.
9-bit ADC Prescaler
Clk
ADC
PRESCALER[2:0]
CL
K/4
CL
K/8
CL
K/1
6
CL
K/3
2
CL
K/6
4
CL
K/1
2
8
Clk
PER
CL
K/2
5
6
CL
K/5
1
2
Propagation Delay =
1
RESOLUTION 1 +
2
-------------------------------------------------
GAIN + +
f
ADC
---------------------------------------------------------------------------------
clk
ADC
START
ADC SAMPLE
IF
CONVERTING BIT 10 9 8 7 6 5 4 3 2 1 lsb
1 2 3 4 5 6 7 8
msb
9