Atmel XMEGA B, User Manual

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254 XMEGA B [DATASHEET]
8291B–AVR–01/2013
19.10.3 STATUS – Status register

Bit 7
–
DIF: Data Interrupt Flag
This flag is set when a data byte is successfully received; i.e., no bus error or collision occurred during the operation.
Writing a one to this bit location will clear DIF. When this flag is set, the slave forces the SCL line low, stretching the TWI
clock period. Clearing the interrupt flags will release the SCL line.
This flag is also cleared automatically when writing a valid command to the CMD bits in the CTRLB register

Bit 6
–
APIF: Address/Stop Interrupt Flag
This flag is set when the slave detects that a valid address has been received, or when a transmit collision is detected. If
the PIEN bit in the CTRLA register is set, a STOP condition on the bus will also set APIF. Writing a one to this bit location
will clear APIF. When set for an address interrupt, the slave forces the SCL line low, stretching the TWI clock period.
Clearing the interrupt flags will release the SCL line.
The flag is also cleared automatically for the same condition as DIF.
 Bit 5
–
CLKHOLD: Clock Hold
This flag is set when the slave is holding the SCL line low.This is a status flag and a read-only bit that is set when DIF or
APIF is set. Clearing the interrupt flags and releasing the SCL line will indirectly clear this flag.

Bit 4
–
RXACK: Received Acknowledge
This flag contains the most recently received acknowledge bit from the master. This is a read-only flag. When read as
zero, the most recent acknowledge bit from the maser was ACK, and when read as one, the most recent acknowledge bit
was NACK.

Bit 3
–
COLL: Collision
This flag is set when a slave has not been able to transfer a high data bit or a NACK bit. If a collision is detected, the
slave will commence its normal operation, disable data, and acknowledge output, and no low values will be shifted out
onto the SDA line. Writing a one to this bit location will clear COLL.
The flag is also cleared automatically when a START or repeated START condition is detected.
 Bit 2
–
BUSERR: TWI Slave Bus Error
This flag is set when an illegal bus condition occurs during a transfer. An illegal bus condition occurs if a repeated START
or a STOP condition is detected, and the number of bits from the previous START condition is not a multiple of nine.
Writing a one to this bit location will clear BUSERR.
For bus errors to be detected, the bus state logic must be enabled. This is done by enabling the TWI master.

Bit 1
–
DIR: Read/Write Direction
The R/W direction (DIR) flag reflects the direction bit from the last address packet received from a master. When this bit
is read as one, a master read operation is in progress. When read as zero, a master write operation is in progress.
 Bit 0
–
AP: Slave Address or Stop
This flag indicates whether a valid address or a STOP condition caused the last setting of APIF in the STATUS register.
Table 19-9. TWI slave address or stop.
Bit 7 6 5 4 3 2 1 0
+0x02
DIF APIF CLKHOLD RXACK COLL BUSERR DIR AP
Read/Write R/W R/W R R R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
AP Description
0 A STOP condition generated the interrupt on APIF
1 Address detection generated the interrupt on APIF