Atmel XMEGA B, User Manual

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169 XMEGA B [DATASHEET]
8291B–AVR–01/2013
Table 13-8. Command selections

Bit 1 – LUPD: Lock Update
When this bit is set, no update of the buffered registers is performed, even though an UPDATE condition has occurred.
Locking the update ensures that all buffers, including DTI buffers, are valid before an update is performed.
This bit has no effect when input capture operation is enabled.

Bit 0 – DIR: Counter Direction
When zero, this bit indicates that the counter is counting up (incrementing). A one indicates that the counter is in the
down-counting (decrementing) state.
Normally this bit is controlled in hardware by the waveform generation mode or by event actions, but this bit can also be
changed from software.
13.12.9 CTRLGCLR/CTRLGSET – Control register G Clear/Set
Refer to “CTRLFCLR/CTRLFSET – Control register F Clear/Set” on page 168 for information on how to access this type
of status register.

Bit 7:5 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero
when this register is written.

Bit 4:1 – CCxBV: Compare or Capture x Buffer Valid
These bits are set when a new value is written to the corresponding CCxBUF register. These bits are automatically
cleared on an UPDATE condition.
Note that when input capture operation is used, this bit is set on a capture event and cleared if the corresponding CCxIF
is cleared.

Bit 0 – PERBV: Period Buffer Valid
This bit is set when a new value is written to the PERBUF register. This bit is automatically cleared on an UPDATE
condition.
CMD Group Configuration Command Action
00 NONE None
01 UPDATE Force update
10 RESTART Force restart
11 RESET Force hard reset (ignored if T/C is not in OFFstate)
Bit 7 6 5 4 3 2 1 0
+0x0A/ +0x0B
– – – CCDBV CCCBV CCBBV CCABV PERBV
Read/Write R R R R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0