259
XMEGA B [DATASHEET]
8291B–AVR–01/2013
Table 20-1. SPI pin override and directions.
20.3
Master Mode
In master mode, the SPI interface has no automatic control of the SS line. If the SS pin is used, it must be configured as
output and controlled by user software. If the bus consists of several SPI slaves and/or masters, a SPI master can use
general purpose I/O pins to control the SS line to each of the slaves on the bus.
Writing a byte to the DATA register starts the SPI clock generator and the hardware shifts the eight bits into the selected
slave. After shifting one byte, the SPI clock generator stops and the SPI interrupt flag is set. The master may continue to
shift the next byte by writing new data to the DATA register, or can signal the end of the transfer by pulling the SS line
high. The last incoming byte will be kept in the buffer register.
If the SS pin is not used and is configured as input, it must be held high to ensure master operation. If the SS pin is set as
input and is being driven low, the SPI module will interpret this as another master trying to take control of the bus. To
avoid bus contention, the master will take the following action:
1.
The master enters slave mode.
2.
The SPI interrupt flag is set.
20.4
Slave Mode
In slave mode, the SPI module will remain sleeping with the MISO line tri-stated as long as the SS pin is driven high. In
this state, software may update the contents of the DATA register, but the data will not be shifted out by incoming clock
pulses on the SCK pin until the SS pin is driven low. If SS is driven low, the slave will start to shift out data on the first
SCK clock pulse. When one byte has been completely shifted, the SPI interrupt flag is set. The slave may continue
placing new data to be sent into the DATA register before reading the incoming data. The last incoming byte will be kept
in the buffer register.
When SS is driven high, the SPI logic is reset, and the SPI slave will not receive any new data. Any partially received
packet in the shift register will be dropped.
As the SS pin is used to signal the start and end of a transfer, it is also useful for doing packet/byte synchronization,
keeping the slave bit counter synchronous with the master clock generator.
20.5
Data Modes
There are four combinations of SCK phase and polarity with respect to serial data. The SPI data transfer formats are
shown in
. Data bits are shifted out and latched in on opposite edges of the SCK signal, ensuring sufficient
time for data signals to stabilize.
The leading edge is the first clock edge of a clock cycle. The trailing edge is the last clock edge of a clock cycle.
Pin
Master Mode
Slave Mode
MOSI
User defined
Input
MISO
Input
User defined
SCK
User defined
Input
SS
User defined
Input
Summary of Contents for XMEGA B
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