81
XMEGA B [DATASHEET]
8291B–AVR–01/2013
7.4.2.3 32.768kHz Crystal Oscillator
A 32.768kHz crystal oscillator can be connected between the TOSC1 and TOSC2 pins and enables a dedicated low
frequency oscillator input circuit. A typical connection is shown in
. A low power mode with reduced
voltage swing on TOSC2 is available. This oscillator can be used as a clock source for the system clock, RTC and LCD,
and as the DFLL reference clock.
Figure 7-4.
32.768kHz crystal oscillator connection.
Two capacitors, C1 and C2, may be added to match the required load capacitance for the connected crystal. For details
on recommened TOSC characteristics and capacitor laod, refer to device datasheets.
7.5
System Clock Selection and Prescalers
All the calibrated internal oscillators, the external clock sources (XOSC), and the PLL output can be used as the system
clock source. The system clock source is selectable from software, and can be changed during normal operation. Built-in
hardware protection prevents unsafe clock switching. It is not possible to select a non-stable or disabled oscillator as the
clock source, or to disable the oscillator currently used as the system clock source. Each oscillator option has a status
flag that can be read from software to check that the oscillator is ready.
The system clock is fed into a prescaler block that can divide the clock signal by a factor from 1 to 2048 before it is routed
to the CPU and peripherals. The prescaler settings can be changed from software during normal operation. The first
stage, prescaler A, can divide by a factor of from 1 to 512. Then, prescalers B and C can be individually configured to
either pass the clock through or combine divide it by a factor from 1 to 4. The prescaler guarantees that derived clocks
are always in phase, and that no glitches or intermediate frequencies occur when changing the prescaler setting. The
prescaler settings are updated in accordance with the rising edge of the slowest clock.
Figure 7-5.
System clock selection and prescalers.
Prescaler A divides the system clock, and the resulting clock is clk
PER4
. Prescalers B and C can be enabled to divide the
clock speed further to enable peripheral modules to run at twice or four times the CPU clock frequency. If Prescalers B
and C are not used, all the clocks will run at the same frequency as the output from Prescaler A.
The system clock selection and prescaler registers are protected by the configuration change protection mechanism,
employing a timed write procedure for changing the system clock and prescaler settings. For details, refer to
“Configuration Change Protection” on page 14
.
C1
C2
TOSC2
TOSC1
GND
Prescaler A
1, 2, 4, ... , 512
Prescaler B
1, 2, 4
Prescaler C
1, 2
Internal 2MHz Osc.
Internal 32.768kHz Osc.
Internal 32MHz Osc.
External Oscillator or Clock.
Clk
CPU
Clock Selection
Clk
PER
Clk
SYS
Clk
PER2
Clk
PER4
Internal PLL.
Summary of Contents for XMEGA B
Page 320: ...320 XMEGA B DATASHEET 8291B AVR 01 2013 Table 25 12 7 segments Character Table...
Page 321: ...321 XMEGA B DATASHEET 8291B AVR 01 2013 Table 25 13 14 segments Character Table...
Page 322: ...322 XMEGA B DATASHEET 8291B AVR 01 2013 Table 25 14 16 segments Character Table...
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