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Virtex-4 QV FPGA Ceramic Packaging
UG496 (v1.1) June 8, 2012
Chapter 2: Pinout Tables
R
102
AVCCAUXRXA_102
B32
102
RXPPADA_102
A31
102
VTRXA_102
C34
102
RXNPADA_102
A32
102
AVCCAUXMGT_102
J33
102
AVCCAUXTX_102
F33
102
VTTXA_102
D33
102
TXPPADA_102
D34
102
TXNPADA_102
E34
102
VTTXB_102
G33
102
TXPPADB_102
F34
102
TXNPADB_102
G34
102
AVCCAUXRXB_102
K33
102
RXPPADB_102
J34
102
VTRXB_102
H34
102
RXNPADB_102
K34
102
MGTCLK_P_102
M34
102
MGTCLK_N_102
N34
103
AVCCAUXRXA_103
T33
103
RXPPADA_103
R34
103
VTRXA_103
U34
103
RXNPADA_103
T34
103
AVCCAUXMGT_103
AC33
103
AVCCAUXTX_103
Y33
103
VTTXA_103
V33
103
TXPPADA_103
V34
103
TXNPADA_103
W34
103
VTTXB_103
AA33
103
TXPPADB_103
Y34
103
TXNPADB_103
AA34
103
AVCCAUXRXB_103
AE33
103
RXPPADB_103
AC34
103
VTRXB_103
AB34
103
RXNPADB_103
AD34
Table 2-2:
CF1144 Package(FX60) (Cont’d)
Bank
Pin Description
Pin
Number
No Connects