Xilinx Virtex-4 QV FPGA, Руководство пользователя

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92 www.xilinx.com Virtex-4 QV FPGA Ceramic Packaging
UG496 (v1.1) June 8, 2012
Chapter 2: Pinout Tables
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10 IO_L22N_10 R6
10 IO_L23P_VRN_10 N4
10 IO_L23N_VRP_10 P4
10 IO_L24P_CC_LC_10 R8
10 IO_L24N_CC_LC_10 R7
10 IO_L1P_10 N12
10 IO_L1N_10 M11
10 IO_L2P_10 M10
10 IO_L2N_10 N10
10 IO_L3P_10 G7
10 IO_L3N_10 H7
10 IO_L4P_10 L8
10 IO_L4N_VREF_10 M7
10 IO_L5P_10 P11
10 IO_L5N_10 R11
10 IO_L6P_10 J6
10 IO_L6N_10 K6
10 IO_L7P_10 P12
10 IO_L7N_10 R12
10 IO_L8P_CC_LC_10 G3
10 IO_L8N_CC_LC_10 H3
10 IO_L9P_CC_LC_10 G6
10 IO_L9N_CC_LC_10 G5
10 IO_L10P_10 P10
10 IO_L10N_10 P9
10 IO_L11P_10 K8
10 IO_L11N_10 K7
10 IO_L12P_10 H4
10 IO_L12N_VREF_10 J4
10 IO_L13P_10 H5
10 IO_L13N_10 J5
10 IO_L14P_10 L5
10 IO_L14N_10 M5
10 IO_L15P_10 N9
10 IO_L15N_10 N8
10 IO_L16P_10 K3
10 IO_L16N_10 L3
10 IO_L25P_CC_LC_10 T11
Table 2-3: FF1517 Package Pinout (FX140) (Cont’d)
Bank Pin Description Pin Number No Connects