42
Virtex-4 QV FPGA Ceramic Packaging
UG496 (v1.1) June 8, 2012
Chapter 2: Pinout Tables
R
N/A
GND
E15
N/A
GND
R15
N/A
GND
W15
N/A
GND
AE15
N/A
GND
H16
N/A
GND
P16
N/A
GND
V16
N/A
GND
AH16
N/A
GND
AP16
N/A
GND
L17
N/A
GND
AA17
N/A
GND
AL17
N/A
GND
D18
N/A
GND
P18
N/A
GND
AD18
N/A
GND
A19
N/A
GND
G19
N/A
GND
U19
N/A
GND
AA19
N/A
GND
AG19
N/A
GND
K20
N/A
GND
T20
N/A
GND
Y20
N/A
GND
AB20
N/A
GND
AK20
N/A
GND
C21
N/A
GND
L21
N/A
GND
N21
N/A
GND
AC21
N/A
GND
AN21
N/A
GND
F22
N/A
GND
K22
N/A
GND
M22
N/A
GND
T22
N/A
GND
Y22
N/A
GND
AD22
N/A
GND
AF22
N/A
GND
J23
Table 2-1:
CF1140 Package Pinout (SX55) (Cont’d)
Bank
Pin Description
Pin
Number
No Connects