44
Virtex-4 QV FPGA Ceramic Packaging
UG496 (v1.1) June 8, 2012
Chapter 2: Pinout Tables
R
N/A
GND
J33
N/A
GND
W33
N/A
GND
AJ33
N/A
GND
B34
NC
N/A
GND
M34
N/A
GND
AB34
N/A
GND
AM34
N/A
GND
AN34
NC
N/A
VCCAUX
N8
N/A
VCCAUX
F9
N/A
VCCAUX
T9
N/A
VCCAUX
AH9
N/A
VCCAUX
J10
N/A
VCCAUX
AA10
N/A
VCCAUX
M11
N/A
VCCAUX
AD11
N/A
VCCAUX
AG12
N/A
VCCAUX
U16
N/A
VCCAUX
AJ16
N/A
VCCAUX
Y17
N/A
VCCAUX
R18
N/A
VCCAUX
F19
N/A
VCCAUX
V19
N/A
VCCAUX
H23
N/A
VCCAUX
L24
N/A
VCCAUX
AC24
N/A
VCCAUX
P25
N/A
VCCAUX
AF25
N/A
VCCAUX
G26
N/A
VCCAUX
W26
N/A
VCCAUX
AJ26
N/A
VCCAUX
AB27
N/A
VCCINT
K7
N/A
VCCINT
AB7
N/A
VCCINT
AF9
N/A
VCCINT
L10
Table 2-1:
CF1140 Package Pinout (SX55) (Cont’d)
Bank
Pin Description
Pin
Number
No Connects