150
Virtex-4 QV FPGA Ceramic Packaging
UG496 (v1.1) June 8, 2012
Chapter 2: Pinout Tables
R
16
VCCO_16
AA7
16
VCCO_16
AB14
16
VCCO_16
AB4
16
VCCO_16
AC1
16
VCCO_16
AC11
16
VCCO_16
AD8
16
VCCO_16
AE5
16
VCCO_16
AF2
16
VCCO_16
W3
N/A
AV19
N/A
VREFP_SM
AV20
N/A
AVDD_SM
AW21
N/A
VN_SM
AW19
N/A
VP_SM
AW20
N/A
AVSS_SM
AV18
N/A
B20
N/A
VREFP_ADC
B21
N/A
AVDD_ADC
B22
N/A
VN_ADC
A20
N/A
VP_ADC
A21
N/A
AVSS_ADC
A19
N/A
GND
B1
NC
N/A
GND
H1
N/A
GND
V1
N/A
GND
AH1
N/A
GND
AV1
NC
N/A
GND
A2
NC
N/A
GND
B2
N/A
GND
L2
N/A
GND
AA2
N/A
GND
AL2
N/A
GND
AV2
N/A
GND
AW2
NC
N/A
GND
D3
N/A
GND
P3
Table 2-4:
CF1509 Package Pinout (LX200) (Cont’d)
Bank
Pin Description
Pin Number
No Connect