Siemens C541U, Руководство пользователя

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Semiconductor Group 6-60 1999-04-01
On-Chip Peripheral Components
C541U
DINIT Device initialization in progress
At the end of a software reset, bit DINIT is set by hardware. After software reset
of the USB module, the USB module must be initialized by the CPU. When DINIT
is set after a software reset, 5 bytes for each endpoint must be written to SFR
USBVAL. After the 25th byte, bit DONE0 has to be set by software. Bit DINIT is
reset by hardware after a successful initialization sequence.
RSM Resume bus activity
When the USB device is in suspend mode, setting bit RSM resumes bus activity
of the device. In response to this action, the USB will disassert the suspend bit and
will perform the remote wake-up operation. Writing 0 to RSM has no effect, the bit
is reset if bit SUSP is 0.
UCLK UDC clock selection
Bit UCLK controls the functionality of the USB core clock in full speed mode
(SPEED=1) as well as in low speed mode (SPEED=0)..
If UCLK=0, the USB core clock (48 MHz or 6 MHz) is disabled.
If UCLK=1, the USB core clock (48 MHz or 6 MHz) is enabled.
PCLK PLL clock select
Bit PCLK controls the 48 MHz PLL.
If PCLK=0, the 48 MHz PLL is disabled (default after reset).
If PLCK=1, the 48 MHz PLL is enabled.
For power consumption and EMI reasons, the 48 MHz PLL should be disabled in
low speed mode (SPEED=0).
Bit Function