Schweitzer Engineering Laboratories SEL-700G Series, Инструкция по эксплуатации, Страница: 223 / 824

4.117
Date Code 20170814 Instruction Manual SEL-700G Relay
Protection and Logic Functions
Group Settings (SET Command)
Note in Figure 4.85 and Figure 4.87 that the assertion of internal enable
DIRQE (for the negative-sequence voltage-polarized directional element)
disables the positive-sequence voltage-polarized directional element. The
negative-sequence voltage-polarized directional element has priority over the
positive-sequence voltage-polarized directional element in controlling the phase
overcurrent elements. The negative-sequence voltage-polarized directional element
operates for unbalanced faults, while the positive-sequence voltage-polarized
directional element operates for three-phase faults.
Note also in Figure 4.87 that the assertion of ZLOAD disables the positive-
sequence voltage-polarized directional element. ZLOAD asserts when the
relay is operating in a user-defined load region (see Figure 4.94).
Directional Element Routing
Refer to Figure 4.85 and Figure 4.88. The directional element outputs are
routed to the forward (Relay Word bits DIRQF and DIRPF) and reverse
(Relay Word bits DIRQR and DIRPR) logic points and then on to the
direction forward/reverse logic in Figure 4.89 and Figure 4.90.
Loss-of-Potential
If a loss-of-potential condition occurs (Relay Word bit LOP asserts), then the
forward logic points (Relay Word bits DIRQF and DIRPF) assert to logical 1,
thus enabling the negative-sequence and phase overcurrent elements that are
set direction forward (with settings DIR1 = F, DIR2 = F). These direction
forward overcurrent elements effectively become nondirectional and provide
overcurrent protection during a loss-of-potential condition.
As detailed previously (in Figure 4.74 and Figure 4.87), voltage-based
directional elements are disabled during a loss-of-potential condition. Thus,
the overcurrent elements controlled by these voltage-based directional
elements are also disabled. But this disable condition is overridden for the
overcurrent elements set direction forward if setting EFWDLOP := Y.
Refer to Figure 4.120 and the accompanying text for more information on
loss-of-potential.
Direction Forward/Reverse Logic
Refer to Figure 4.85, Figure 4.89, and Figure 4.90. The forward (Relay Word
bits DIRQF and DIRPF) and reverse (Relay Word bits DIRQR and DIRPR)
logic points are routed to the different levels of overcurrent protection by the
level direction settings DIR1 and DIR2.
Table 4.33 shows the overcurrent elements that are controlled by each level
direction setting. Note in Table 4.33 that all the time-overcurrent elements
(51_T elements) are controlled by the DIR1 level direction setting.
If a level direction setting (for example, DIR1) is set:
DIR1 :=
N
(nondirectional)
then the corresponding Level 1 directional control outputs in Figure 4.89 and
Figure 4.90 assert to logical 1. The referenced Level 1 overcurrent elements in
Figure 4.89 and Figure 4.90 are not controlled by the directional control logic.
See Directional Control Settings on page 4.121 for a discussion of the
operation of level direction settings DIR1 and DIR2 when the directional
control enable setting EDIR is set to EDIR := N.
In some applications, level direction settings DIR1 and DIR2 are not flexible
enough in assigning the necessary direction for certain overcurrent elements.