Chapter 2: Introduction
48
UL I2C Bus Operation
The Zircon UL provides two I2C ports, each port having master and slave capability. A master-
slave port contains a master engine and a slave engine where each engine contains one 8-byte
deep physical FIFO used for sending (TX) and receiving (RX) bytes to and from the I2C bus.
For the FIFO of each master and slave engine, hardware generates a set of FIFO status flags
that are relevant when the FIFO is receiving data, and a separate set of status flags that are
relevant when the FIFO is transmitting data.
When an engine is transferring data over the I2C bus, the master or the slave automatically
extends the low period of SCL (clock-stretch) on the I2C bus in the following situations:
•
By the master when the master TX FIFO becomes empty during a master write transaction
•
By the slave when it receives a byte during a write access but the slave RX FIFO is already full
•
By the slave after every byte it receives, if the slave RX FIFO has not been enabled. In this
configuration, the slave is processing received bytes on a byte-by-byte basis, giving firmware the
opportunity to evaluate bytes on a byte-by-byte basis.
Slave address decoding can be enabled for secondary and broadcast (general call) addresses
as defined by the I2C specification
I2C0 PM Implementation
In the PM implementation, I2C0 is assigned to the IPMB and is used to receive commands
from system IPMI controller. The operational specifications for the IPMB are contained in the
CompactPCI System Management Specification PICMG 2.9
. The interface circuit on the UL
was designed to conform to these specifications and operates as a Peripheral Manager (PM)
on the IPMB. Refer to the
Zircon UL Programmers Hardware Reference Manual
for further
information.
The Zircon UL processes commands and operations conforming to the IPMI protocol. See
“IPMI Commands,” on page 50
for a list of those commands and operations supported by PM
implementation.
I2C1 PM Implementation
In the PM implementation, I2C1 is assigned to the local I2C bus and is used to communicate
with on-board control peripherals, blade sensors and the blade host processor. The electrical
operational specifications for the local I2C bus are similar to the IPMB. These specifications are
contained in the
CompactPCI System Management Specification PICMG 2.9
and for the most
part can be used to implement the local bus. The major departure from the specification is that
the local bus operates at 400 KHz (vs. 100 KHz for IPMB) and the UL operates in a manner
similar to the baseboard management controller (BMC). Refer to the
Zircon UL Programmers
Hardware Reference Manual
for further information.
I2C1
The Zircon UL issues commands and operations conforming to the IPMI protocol for standard
services already defined in the IPMI protocol. See
“IPMI Custom Commands,” on page 52
for a
list of those commands and operations supported by PM implementation. In addition to this a
set of custom commands and operations are implemented to support blade-specific commands
and operations. See
“IPMI Bus Supported Commands,” on page 50
for specific information.
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