Chapter 2: Introduction
18
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DXI
•
ISUP
•
LAN/WAN data transport
The main processor, an AMCC 440GX, runs at 800 MHz. The AMCC 440GX is an embedded
RISC processor with integrated modules that provide interfaces for:
•
The local 33 MHz, 32-bit PCI bus
•
Dual UARTs
•
10/100/1G data rate Ethernet RGMII
•
An on-chip Double Data Rate (DDR) SDRAM controller
On-board memory consists of:
•
512 MB of 166 MHz DDR SDRAM with ECC
•
8 MB boot flash
•
128 MB of application flash
A 10/100/1G unmanaged Ethernet switch interfaces to the AMCC 440GX’s RGMII Ethernet
ports. The Ethernet switch provides seven ports of 10/100/1G Base-T routing and connectivity
to:
•
The PICMG 2.16 CompactPCI packet switching backplane
•
Two PTMC mezzanine slots
•
RJ45 connectors on the front and rear panel faceplates
Three IDT 82P2288 T1/E1/J1 octal transceivers integrate eight universal T1/E1/J1 Line
Interface Units (LIU) and eight framers in a single monolithic device. Egress and ingress spans
to and from the network side are coupled into the transceiver’s receive and transmit ports and
pass through the built-in impedance terminations. In T1/J1 mode, the recovered data and clock
of each link can be configured in the following formats:
•
Super Frame (SF)
•
Extended Super Frame (ESF)
•
T1 Digital Multiplexer (DM)
•
Switch Line Carrier - 96 (SLC-96)
A Zarlink MT90866 digital timeslot switch provides switching capacities of:
•
4,096 x 2,432 channels between the H.110 backplane and the CPC324’s local streams
•
2,432 x 2,432 channels among local streams
•
2,048 x 2,048 channels among backplane streams
Minimal host supervision is required for the three Mindspeed CN8478 eight-port Multichannel
Synchronous Communications Controllers (MUSYCC) that manage linked lists of channel data
buffers in host memory by performing Direct Memory Access (DMA) on HDLC channels.
MUSYCC operates at Layer 2 of the Open Systems Interconnection (OSI) protocol reference
model. Each MUSYCC interfaces to 256 TS data streams from the Zarlinks local TDM side.
Processed data is transferred across the 32-bit local PCI bus to system memory.
Two sets of PTMC slot locations are provided for two single or one dual PTMC (PCI Telecom
Mezzanine Card) module. See
Figure 2-1, “CPC324 Front Panel,” on page 19
for locations.
The PTMC
interfaces are identical and support the following under PICMG 2.15 PTMC
configuration 2:
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