Chapter 2: Introduction
34
As mentioned above, the DPLL can choose from several input sources to obtain the signal it
needs to lock to. This mechanism is what supplies the system synchronization. These clock
sources can be selected via the reference mux internal to the part (LREF0…LREF6).
Internal Reference Clock Sources
The internal reference selector mux for the DPLL has a redundant configuration. The primary
and secondary muxes both have access to the same set of clock sources. These sources
include any of the eight local reference inputs, the A and B CT bus clocks or the CT Net
references from the CT bus.
Internal Reference Monitors
There are two reference monitor circuits: one for the primary reference (PRI_REF) and one for
the secondary reference (SEC_REF). These two circuits monitor the selected input reference
signals and detect failures by setting up the adequate internal fail outputs (FAIL_PRI and
FAIL_SEC). These fail signals are used in the autodetect mode as the internal LOS_PRI and
LOS_SEC signals to indicate when the reference is failed. The method of generating failure
depends on the selected reference:
•
For all references, the "minimum 90 ns" check is made. This is the requirement by the H110
specifications. Both low level and high level of the reference must last for a minimum of 90 ns each.
•
The "period in the specified range" check is done for all references. The length of the period of the
selected input reference is checked if it is in the specified range. For the E1 (2.048 MHz clock) or the
T1 (1.544 MHz clock) reference, the period of the clock can vary within the range of 1
±
1/4 of the
defined clock period (488 ns for the E1 clock and 648 ns for T1 clock). For the 8 KHz reference, the
variation is from 1
±
1/32 period.
•
If the selected reference is E1 or T1, the "64 periods in the specified range" check is made. The
selected reference is observed for long period (64 reference clock cycles) and checked if it is within
the specified range - from 62 to 66 clock periods.
These reference signal verifications include a complete loss or a large frequency shift of the
selected reference signal. When the reference signal returns to normal, the LOS_PRI and
LOS_SEC signals return to logic low.
Jitter Transfer
Rate limited by Phase Slope Limiter to 4.6 ns/125 µs.
Jitter Transfer Function Cutoff frequency 1.52 Hz with slope of 20
db/decade. Refer to the datasheet for the actual curves and the UI
calculations.
Frequency Accuracy
Master Clock/ppm + DPLL/ppm= 25+.03=25.03 ppm of selected
frequency.
Holdover accuracy
Same as above calculation
Locking Range
±273 ppm
Maximum Time Interval Error (MTIE)
21 ns for every reference switch.
Phase Continuity
Maintained to within 4.6 ns at the instance (over one frame) of all
reference switches.
Phase Lock Time
Less than 25 seconds
Table 2-5:
H.110 DPLL Operating Specifications (Continued)
Parameter
Value
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