Chapter 2: Introduction
46
Power Distribution
The power input block consists of the backplane power connections, voltage regulators for
operating, I/O and core voltages and a 3.3 V power monitor. See
Figure 2-11, “Power
Distribution Block Diagram,”
below.
Figure 2-11:
Power Distribution Block Diagram
The primary power is sourced from the CompactPCI VSM pin on J1-A4. The VSM power is +5V
at 100 mA steady state, 500 mA peak. The 140 mA PTC fuse provides the PICMG 2.9 required
overcurrent protection circuit in the VSM supply. The power is diode ORed with the backplane
+5V supply to provide an alternate power source when VSM is not available. This may occur in
a non-2.9 compliant backplane.
The power is then routed to a Linear Tech 1963 low dropout linear regulator rated at 1.5 A. This
regulator supplies the 3.3V I/O power for the Zircon UL as well as the operating power for the
rest of the PM circuitry. This voltage in turn is fed into a Micrel 5213 linear regulator rated at
80 mA, that creates a 2.5V supply for the Zircon UL core voltage.
Zircon UL ARM7 CPU
The QLOGIC Zircon UL has an internal ARM7 CPU that is used to execute code contained in
the AM29LV800B flash device. This code contains an operating system based on the Thread-X
real time operating system (RTOS). QLogic supplies a modular application code set that runs
under Thread-X and allows the Zircon UL to conform to the IPMI protocol. The RTOS and the
application code configure most of the internal registers on a default basis. Refer to the
Zircon
UL Technical Manual
and
Zircon UL Programmers Hardware Reference Manual
for more
information on the chip’s default internal settings.
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