CPC324 Functional Blocks
43
Interrupts
The MUSYCC provides an interrupt pin that must be programmed using the interrupts of the
AMCC 440GX processor to use this function. The MUSYCC should be taken out of reset prior
to setting the local enable (or clearing the local mask) of the interrupt.
The interrupts are listed in
Table 2-8, “MUSYCC Interrupt Mapping,”
below.
PCI Initialization
When the AMCC 440GX processor initializes a module containing a PCI device, the software
reads the configuration space of each PCI device on a PCI bus. Hardware signals select a
specific PCI device based on a bus number, a slot number, and a function number. If the
addressed device (via signal lines) responds to the configuration cycle by claiming the bus, that
function’s configuration space is read out from the device during the cycle. Because any PCI
device can be a multifunction device, every supported function’s configuration space must be
read from the device. Based on the information read, the configuration manager assigns
system resources to each supported function within the device. Sometimes new information
must be written to the function’s configuration space; this is accomplished with a configuration
write cycle. MUSYCC is a multifunction device with device-resident memory to store the
required configuration information. MUSYCC supports function 0 and function 1 and, as such,
only responds to function 0 and function 1 configuration cycles, defined as listed below:
•
Function 0: All HDLC processing as an HDLC network controller. Can master the PCI bus or respond
to slave accesses from another bus master.
•
Function 1: EBUS bridge to local devices. Responds only when another bus master performs a
memory access into the function 1 address range.
PCI Bus Operations
MUSYCC behaves either as a PCI master or a PCI slave at any time and switches between
these modes as required during device operation. As a PCI slave, MUSYCC responds to the
following PCI bus operations:
•
Memory read
•
Memory write
•
Configuration read
•
Configuration write
•
Memory read multiple (treated like memory read in slave mode)
•
Memory read line (treated like memory read in slave mode)
•
Memory write and invalidate (treated like memory write)
All other PCI cycles are ignored by MUSYCC. Only memory cycles are mapped to operations
on the EBUS.
Table 2-8:
MUSYCC Interrupt Mapping
MUSYCC
440GX Interrupt Connection
A
IRQ00
B
IRQ01
C
IRQ02
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