Chapter 2: Introduction
44
As a PCI-master, MUSYCC generates the following PCI bus operations:
•
Memory Read Multiple (generated only in master mode)
•
Memory Write
•
Dual Address Cycle
DMA Controller
The DMA controllers (Rx-DMAC and Tx-DMAC) manage all memory operations between a
corresponding BLP and the host interface. DMAC takes requests from BLP to either fill or flush
internal FIFO buffers, sets up an access to data buffers in shared memory, and requests
access to the PCI bus through the host interface.
Interrupt Controller
The interrupt controller takes receive and transmit events from Rx-BLP and Tx-BLP,
respectively. The INTC coordinates the transfer of internally queued descriptors to an interrupt
queue in shared memory and also coordinates the notification to the host of pending interrupts.
Zircon UL Peripheral Monitor
The CPC324 incorporates a Zircon UL RISC microprocessor Intelligent Platform Management
Controller (IPMC) for the support of the Intelligent Platform Management Bus
(IPMB) in a
CompactPCI environment. The IPMB is an I2C-based bus that provides a standardized
interconnection between different boards within a CompactPCI chassis for auxiliary
management of CPCI baseboards.
System management software and the OS can provide a higher level of control, error handling,
and alarms. The IPMC can support monitoring, logging, and control recovery functions
independent of the AMCC 440GX main processor and operating software. The IPMC is used
by IPMC system management software to provide an high level of emergency manageability by
providing access to the IPMI management information and integrating IPMI with the additional
management functions provided by OS management application software.
The IPMC includes support for storing and accessing multiple sets of non-volatile field
replaceable unit (FRU) information for CPC324. The FRU data includes information such as
serial number, part number, and model. IPMC FRU information can be made accessible via the
IPMB and IPMC. FRU information can be retrieved at any time, independent of the AMCC
440GX. This allows FRU information to be retrieved via out-of-band interfaces, such as the
chassis or system management controller, a remote management blade, or other device
connected to the IPMB. FRU information can even be available when the system is powered
down. These abilities allow FRU information to be obtained under failure conditions when FRU
access mechanisms that rely on the main processor become unavailable.
Features:
•
ARM RISC CPU running at 40 MHz
•
16 KB of internal SRAM
•
External non-multiplexed bus supporting 16-bit wide flash memory, 29LV800B-90 implemented as
512Kx16
•
Optional 16-bit wide SRAM, implemented as 512Kx16 (for debug and trouble shooting only)
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