Chapter 2: Introduction
30
T1/E1/J1 Framers and LIU
Three IDT 82P2288 octal transceivers provide framing and line interface functionality for 24-
port connectivity on 24 T1, E1 or J1 telecom trunks. Each octal transceiver has the capability of
providing any two of eight recovered clocks to the local reference (LREF) inputs of the Zarlink
H.110 switch. The recovered clocks are 1.544 MHz in T1/J1 applications and 2.048 MHz in E1
applications.
IDT 82P2288 General Specifications
The IDT 82P2288 transceiver meets the requirements of ITU, ETSI and AT&T jitter
specifications. The high level of integration eliminates external components for line
equalization. Integrated jitter attenuators (JAT) are incorporated in both the transmit and
receive directions of each channel. Dual JATs allow the 82P2288 transceiver to simultaneously
reduce jitter from both the line and system clocks.
IDT 82P2288 features include:
•
Links configuration as T1, E1 or J1
•
Frame alignment/generation for T1 (per ITU-T G.704, TA-TSY-000278, TR-TSY-000008), E1 (per
ITU-T G.704), J1 (per JT G.704) and un-framed mode
•
Supports T1/J1 Super Frame and Extended Super Frame, T1 Digital Multiplexer and Switch Line
Carrier - 96, E1 CRC Multi-frame and Signaling Multi-Frame
•
Signaling extraction/insertion for CAS and RBS signaling
Framer Board Level Integration
The three framers serve as the line side receivers for the T1, E1 or J1 external interfaces. Each
framer has eight transmit and receive pairs associated with it. They transform the external data
formats to a common Time Domain Multiplexed (TDM) digital standard signal that is fed to an
on-board TDM switch. There the channels can be routed to the PTMC slots for further signal
processing, to the H.110 CompactPCI backplane connection for offboard processing, or to the
on-board, multi-channel, data communication transceiver for data termination or sourcing. See
Figure 2-5, “Framer Block Diagram,” on page 31
for more information.
Line Receive Signal Path
Receive path signals from the line side are coupled into the RTIPn and RRINGn pins of the line
interface unit (LIU) and pass through an internal programmable receive impedance terminator.
There is a single resistor of 120 ohms external to the part to terminate the receive pair. The
internal programmable adjustment is used to set the exact line termination conditions
depending on the interface standard desired. An adaptive equalizer is provided to increase the
sensitivity for small signals. Internal registers in the framer handle all other line conditioning
requirements needed for the incoming signals. The registers are accessed over the CPU’s
general-purpose bus.
The receive path data through the framer allows recovered data and clock of each link can be
decoded in Super Frame (SF), Extended Super Frame (ESF), T1 Digital Multiplexer or Switch
Line Carrier - 96 (SLC-96) formats. The T1 DM and SLC-96 formats exist only in T1 mode. The
de-framing can also be bypassed to receive in unframed mode.
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