CPC324 Functional Blocks
47
Flash Memory
The memory block consists of an AM 29LV800B-90 flash device from the Spansion line of
Advanced Micro Devices (AMD). It has a 512Kx16 bit data configuration, which is also the
maximum address capability of the Zircon’s external bus for an individual chip selection. The
memory read mode access time is 90 ns maximum. The flash is physically located in a 48-pin
TSOP surface mount package on the secondary (bottom) side of the PCB. For additional
information, refer to the AMD’s
Am29LV800B Spansion Datasheet
.
For the IPMI application, the flash is powered from 3.3V provided by the PM power distribution
block. The flash is directly controlled by the Zircon UL’s parallel interface control lines. There
are, however, two exceptions to this:
The first is the flash’s RESET# input control. This line is the logical OR of the CPU’s reset
output and the ADM1026 I2C peripheral. This input is designed to protect the flash device from
an accidental erasure or overwrite during power up and power down events.
The second exception is the write protect bit (PMWP). When set high, this bit prevents the flash
from being written under any circumstances. The PMWP bit is controlled by an output from the
ADM1026 peripheral located on the local I2C bus. The default signal’s reset state automatically
disables writing.
Figure 2-12:
Flash Device Implementation
The PMFLRDY# control signal connects to the GPIO bit 17 input on the Zircon UL. When set
low, it indicates that the flash is doing an extended time internal operation, such as a block
erasure. When high, it indicates that the flash’s internal controller is idle or has completed a
long-term operation.
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