CPC324 Functional Blocks
45
•
Two identical master/slave I2C supporting a variety of bus speed modes
•
One I2C interface supports the IPMB backplane connection
•
One I2C interface supports the local resources and Local CPU communication connection. Bus is
3.3V, 7-bit addressing at 400 KHz clock rate.
•
Three general-purpose timers, one with watchdog capabilities that can interrupt or reset the ARM
CPU
•
Six analog comparators referenced to an internal 1.2V source
•
18 general purpose/dual function I/Os, some with interrupting capability
•
GPIO17-14 have interrupting capabilities
•
Local I2C peripherals
•
ADM1026 I2C management controller
•
1Mbit EEPROM
•
QS384 used for I2C bus isolator
Figure 2-10, “Zircon UL Block Diagram,”
shows the top-level functional blocks of the Zircon UL.
The following topics explain each functional block and contain any setup and configuration
information associated with that block.
Figure 2-10:
Zircon UL Block Diagram
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