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3-4-6
FAL (Failure Alarm) Area
A 2-digit BCD FAL code is output to bits 25300 to 25307 when the FAL or
FALS instruction is executed. These codes are user defined for use in error
diagnosis, although the PC also outputs FAL codes to these bits, such as one
caused by battery voltage drop.
This area can be reset by executing the FAL instruction with an operand of
00 or by performing a Failure Read Operation from the Programming Con-
sole.
3-4-7
Low Battery Flag
SR bit 25308 turns ON if the voltage of the RAM Unit or CPU11-E backup
battery drops. The ALARM/ERROR indicator on the front of the CPU will also
flash.
AR bit 2404 is a separate Low Battery Flag for the CPU11-E only. It is there-
fore possible to determine which backup battery is low, that of the RAM Unit
or CPU11-E, by checking the status of AR 2404.
This bit can be programmed to activate an external warning for a low battery
voltage.
The Set System instruction (SYS(49)) can be used to turn off the operation of
the battery alarm if desired, e.g., when DM 1000 to DM 1999 is placed in
ROM and a battery is not used in operation. Refer to Section 5 Instruction
Set for details.
3-4-8
Cycle Time Error Flag
SR bit 25309 turns ON if the cycle time exceeds 100 ms. The ALARM/ER-
ROR indicator on the front of the CPU will also flash. Program execution will
not stop, however, unless the maximum time limit set for the watchdog timer
is exceeded. Timing may become inaccurate after the cycle time exceeds
100 ms.
3-4-9
I/O Verification Error Flag
SR bit 25310 turns ON when the Units mounted in the system disagree with
the I/O table registered in the CPU. The ALARM/ERROR indicator on the
front of the CPU will also flash, but PC operation will continue.
To ensure proper operation, PC operation should be stopped, Units checked,
and the I/O table corrected whenever this flag goes ON.
3-4-10
First Cycle Flag
SR bit 25315 turns ON when PC operation begins and then turns OFF after
one cycle of the program. The First Cycle Flag is useful in initializing counter
values and other operations. An example of this is provided 5-12 Timer and
Counter Instructions.
3-4-11
Clock Pulse Bits
Five clock pulses are available to control program timing. Each clock pulse
bit is ON for the first half of the rated pulse time, then OFF for the second
half. In other words, each clock pulse has a duty factor of 50%.
These clock pulse bits are often used with counter instructions to create tim-
ers. Refer to 5-12 Timer and Counter Instructions for an example of this.
Pulse width
1 min
0.02 s
0.1 s
0.2 s
1.0 s
Bit
25400
25401
25500
25501
25502
SR Area
Section 3-4
Содержание SYSMAC C200H
Страница 1: ...OPERATION MANUAL C200H CPU01 E 03 E 11 E SYSMAC Programmable Controllers Cat No W130 E1 05 ...
Страница 2: ...C200H Programmable Controllers CPU01 E 03 E 11 E Operation Manual Revised June 2003 ...
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Страница 8: ...TABLE OF CONTENTS ix Glossary 345 Index 363 Revision History 369 ...
Страница 342: ...336 Programmer Program Date Page Word Contents Notes Word Contents Notes Data Storage ...
Страница 374: ...Cat No W130 E1 05 C200H Programmable Controllers CPU01 E 03 E 11 E OPERATION MANUAL ...