159
Process and Application Parameters [300]
Section 11-3
Note
It is important that the system has reached a stable situation before the
Steady State Test is initiated.
Communication information
PID Steady State Margin [389]
PID steady state margin defines a margin band around the reference that
defines “steady state operation”. During the steady state test the PID opera-
tion is overruled and the VSD is decreasing the speed as long as the PID
error is within the steady state margin. If the PID error goes outside the steady
state margin the test failed and normal PID operation continues, see example.
Communication information
Example: The PID Steady Test starts when the process value [711] is within
the margin and Steady State Test Wait Delay has expired. The PID output will
decrease speed with a step value which corresponds to the margin as long as
the Process value [711] stays within steady state margin. When Min Speed
[341] is reached the steady state test was successful and stop/sleep is com-
manded if PID sleep function [386] and [387] is activated. If the Process value
[711] goes outside the set steady state margins then the test failed and nor-
mal PID operation will continue, see Fig. 84.
Default:
Off
Range:
Off, 0.01–3600 s
Off
A
Modbus Instance no/
DeviceNet no:
43373
Profibus slot/index
170/22
EtherCAT index (hex)
4d2d
Fieldbus format
Long, 1=0.01 s
Modbus format
EInt
Default:
0
Range:
0–10000 in process unit
Modbus Instance no/
DeviceNet no:
43374
Profibus slot/index
170/23
EtherCAT index (hex)
4d2e
Fieldbus format
Long, 1=0.01 s
Modbus format
EInt
0
A
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