NOVA electronics Inc.
MCX514 -
96
－
96
－
2.10
Interrupt
MCX514 has 2 kinds of interruptions, one is the interruption generated from each X, Y, Z and U axis, and the other is the
interruption generated during continuous interpolation driving.
The interrupt signal to the host CPU has also 2 signals, INT0N signal generated from each X, Y, Z and U axis, and INT1N signal
generated during continuous interpolation driving.
All interrupt factors can be set to enable / disable. At reset, all interrupt signals are disabled.
2.10.1 Interrupt from X, Y, Z and U axes
Factors that generate an interrupt from X, Y, Z and U axes are as follows.
Table 2.10-1 Factors of Interrupt from X, Y, Z and U axes
Enable / Disable
WR1 Register
Status RR1
Register
Factors of Interrupt
D0 (CMR0)
D0 (CMR0)
The comparison result of multi-purpose register MR0 with a comparative object
changed to meet the comparison condition.
D1 (CMR1)
D1 (CMR1)
The comparison result of multi-purpose register MR1 with a comparative object
changed to meet the comparison condition.
D2 (CMR2)
D2 (CMR2)
The comparison result of multi-purpose register MR2 with a comparative object
changed to meet the comparison condition.
D3 (CMR3)
D3 (CMR3)
The comparison result of multi-purpose register MR3 with a comparative object
changed to meet the comparison condition.
D4(D-STA)
D4(D-STA)
Driving starts.
D5(C-STA)
D5(C-STA)
Pulse output starts at constant speed area in acceleration / deceleration driving.
D6(C-END)
D6(C-END) Pulse output is finished at constant speed area in acceleration / deceleration driving.
D7(D-END)
D7(D-END) Driving is finished.
D8(H-END)
D8(H-END) Automatic home search is finished.
D9(TIMER)
D9(TIMER)
Timer expires.
D10(SPLTP)
Outputs split pulse. (in positive logic, occurs at
↑ of split pulse)
D11(SPLTE)
Split pulse is finished.
D12(SYNC0)
Synchronous action SYNC0 is activated.
D13(SYNC1)
Synchronous action SYNC1 is activated.
D14(SYNC2)
Synchronous action SYNC2 is activated.
D15(SYNC3)
Synchronous action SYNC3 is activated.
■
Interrupt setting and reading
Each factor of interrupt can be set by setting levels in WR1 register bits: 1- enable and 0 - disable as shown in the table above.
When the interrupt factor that is enabled becomes True, the corresponding bit of RR1 register will be set to 1 and the interrupt
output signal (INT0N) will be on the Low level. After the RR1 status has been read from the host CPU, RR1 register will be
cleared from 1 to 0 and INT0N will return to the Hi-Z level. That is, the interrupt signal is automatically cleared by reading RR1
register. And the information that an interrupt occurred is sent to the CPU only once by the first reading of RR1 register after the
interrupt, and after that, if the user reads RR1 register, the bit indicates 0 unless the next interrupt factor becomes True (Read-reset
method).
■
Multiple interrupts
When multiple interrupt factors are enabled, if the first interrupt factor becomes True, the signal (INT0N ) will be on the Low and
the corresponding bit of RR1 register will be set to 1. After that, if the other factor becomes True before the CPU reads RR1
register, the bit corresponding to the other factor will be set to 1. In this case when reading RR1 register, two or more bits indicate
1 and the each interrupt factor notifies the occurrence of it.
