Nova Electronics MCX514, Руководство пользователя

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NOVA electronics Inc. MCX514 -
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11. Timing of Input / Output Signals
11.1
Power-On Reset
a. The reset signal input to pin RESETN needs to keep on the Low level for at least 8 CLK cycles.
b.
When RESETN is on the Low level for 6 CLK cycles maximum, the power-on output signal is determined to the level shown in
the figure above.
c.
For a maximum of 4 CLK cycles after RESETN is on the Hi level, this IC cannot be read/written.
11.2
Fixed Pulse or Continuous Pulse Driving
1st Pulse 2nd Pulse Final pulse
CLK
WRN
nPP,nPM,
nDRIVE
ASND,
Valid Level
CNST,
Writing a drive command
a
b
c
DSND
nDIR
Valid Level
d
e
nPLS
a
Pre- state
c
a.
Drive status output signal (nDRIVE) is on Hi level after a maximum of 2 CLK cycles from WRN
↑
when a driving command is
written. And it returns to Low level after 1 CLK cycle from when the cycle of final pulse output has finished.
b.
Driving pulses (nPP, nPM and nPLS) shown above are positive logic pulses. The first driving pulse will be output after a
maximum of 4 CLK cycles from WRN
↑
when a driving command is written.
c. ASND, CNST and DSND are on valid level after 3 CLK cycles from nDRIVE
↑
and they return to Low level after 1 CLK cycle
from nDRIVE
↓
.
d. When in 1-pulse 1-direction type, nDIR (direction) signal is valid after 1 CLK cycle from nDRIVE
↑
and keeps its level until
the next command is written after the driving is finished.
e. The first pulse of the drive pulse (nPLS) will be output after 1 CLK cycle from when nDIR (direction) signal is valid.