NOVA electronics Inc. MCX514 -
254
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254
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10.2.3 CLK / Output Signal Timing
The following output signals are synchronized with CLK signal. The level will be changed at CLK
↑
.
CLK
t
DD
Output Signal
Output signals: nPP, nPM, nDCC, nSPLTP, nPIO7
~
0 (according to the function selected)
Symbol
Item
Min.
Max.
Unit
tDD
CLK
↑
→
Output Signal
↑↓
Delay Time
7
30
nS
Output signals: INT0N, INT1N
Symbol
Item
Min.
Max.
Unit
tDD
CLK
↑
→
INT0N, INT1N Signal
↓
Delay Time
12
22
nS
10.2.4 Input Pulses
■
Quadrature Pulses Input Mode (A/B phases)
nECA
nECB
tDE
tDE
tDE
tDE
tDE
tDE
tDE
tDE
Count down
Count up
■
Up / Down Pulses Input Mode
nPPIN
nPMIN
tIH
tIL
tIB
tIH
tIL
tICYC
tICYC
a.
In quadrature pulses input mode, when nECA, nECB input pulses are changed, the value of real position counter will be
reflected in the value of after a maximum of 4 CLK cycles.
b.
In UP/DOWN pulses input mode, the value of real position counter will be reflected in the value of after a maximum of 4 CLK
cycles from nPPIN, nPMIN input
↑
.
Symbol
Item
Min.
Max.
Unit
tDE
n
ECA,
n
ECB
Phase Difference Time
tCYC +20
nS
tIH
n
PPIN,
n
PMIN Hi
Level Width
tCYC +20
nS
tIL
n
PPIN,
n
PMIN Low
Level Width
tCYC +20
nS
tICYC
n
PPIN,
n
PMIN
Cycle
tCYC×2 +20
nS
tIB
n
PPIN
↑
n
PMIN
↑
between Time
tCYC×2 +20
nS
tCYC is a cycle of CLK.