NOVA electronics Inc.
MCX514 -
65
-
65
-
①
nPIOm (m=0~3) signal synchronous pulse output setting
To set nPIOm signal for the synchronous pulse output by mode setting, use PIO signal setting 1 command (21h) and set
as shown below.
WR6
D7
D6
D5
D4
H
L
D15
D14
D13
D12
D11
D10
D9
D8
D3
D2
D1
D0
P1M0 P0M1
P2M0
P3M0
P0M0
P1M1
P2M1
P3M1
nPIO0 Signal
nPIO1 Signal
nPIO2 Signal
nPIO3 Signal
PkM1
PkM0
Setting
k=0
~
3
1
1
Synchronous action output
2 bits of WR6 register corresponding to the nPIOm signal that is used must be set to 1, 1 for the synchronous pulse
output. For instance, when using XPIO2 signal, set D5, D4 bits (P2M1, P2M0) of WR6 register to 1, 1 and then write
PIO signal setting 1 command (21h) with X axis into WR0 register.
②
Logical level of output pulse signal and pulse width settings
To set the logical level of output pulse signal and pulse width, use PIO signal setting 2
・
Other settings (22h) and set as
shown below.
WR6
D7
D6
D5
D4
H
L
D15
D14
D13
D12
D11
D10
D9
D8
D3
D2
D1
D0
P0L
P1L
P2L
P3L
PW0
PW1
PW2
Select pulse width
nPIO3 Pulse signal logic
nPIO2 Pulse signal logic
nPIO1 Pulse signal logic
nPIO0 Pulse signal logic
Specify the logical level of nPIOm signal that is used to D0 to D3 bits (P0L~P3L) of WR6 register. 0 outputs the positive
logic pulse and 1 outputs the negative logic pulse. The bit corresponding to the unused signal should be set to either 0 or
1. And the pulse width shown above must be set to D4 to D6 bits (PW0~PW3) of WR6 register. The settings of WR6
register will be determined by writing PIO signal setting 2
・
Other settings (22h) into WR0 register.
[Note]
•
The setting of pulse width is common in nPIO0~ nPIO3 all signals. It cannot be set to each signal individually.
•
If the synchronous pulse output is activated continuously, when the user tries to activate the next during the
synchronous pulse output, the synchronous pulse does not become inactive and it will output a specified pulse width
again from when the next is activated.
PkL (k=0
~
3)
Pulse signal logic
0
Outputs positive logic pulse
1
Outputs negative logic pulse
PW2 PW1
PW0 Pulse width (CLK=16MHz)
0
0
0
125nsec
0
0
1
312nsec
0
1
0
1μsec
0
1
1
4μsec
1
0
0
16μsec
1
0
1
64μsec
1
1
0
256μsec
1
1
1
1msec