System Register Block
UG0331 User Guide Revision 15.0
680
MM4_5_DDR_FIC_SECURITY
/MM4_5_FIC64_SECURITY
0x128
RO-U
SYSRESET_
N
Read and write security for
masters 4, 5, and DDR_FIC to
eSRAM0, eSRAM1, eNVM1,
eNVM0, and MSS DDR bridge
0x12C
RO-U
SYSRESET_
N
Read and write security for
masters 3, 6, 7, and 8 to
eSRAM0, eSRAM1, eNVM1,
eNVM0, and MSS DDR bridge
0x130
RO-U
SYSRESET_
N
Read and write security for
master 9 to eSRAM0, eSRAM1,
eNVM1, eNVM0, and MSS DDR
bridge
0x134
RO
SYSRESET_
N
Cortex-M3 processor Status
Register
0x138
RO
SYSRESET_
N
ETM count for lower bits [31:0]
0x13C
RO
SYSRESET_
N
ETM count for higher bits
[47:32]
0x140
RO
SYSRESET_
N
Device Status Register
0x144
RO-U
SYSRESET_
N
Configuration for accessibility of
protect regions of eNVM0 and
eNVM1
0x148
RO-U
PORESET_N Code shadow Status Register
0x14C
RO
Configures device version
0x150
RO
MSS DDR PLL Status Register
0x154
RO
SYSRESET_
N
USB Status Register
0x158
RO
SYSRESET_
N
Busy status eNVM0 and eNVM1
Reserved
0x15C
0x160
RO
SYSRESET_
N
MSS DDR bridges status
0x164
RO
PORESET_N DDR I/O Calibration Status
Register
0x168
RO
SYSRESET_
N
MSS DDR Clock Calibration
Status Register
0x16C
RO-P
PORESET_N Configures Watchdog load
value
0x170
RO-P
PORESET_N Configures Watchdog MVRP
value
0x174
RO-P
SYSRESET_
N
User Configuration Register 0
Table 650 •
SYSREG
(continued)
Register Name
Addr.
Offset
Register
Type
Flash
Write
Protect
Reset Source Description
Содержание SmartFusion2 MSS
Страница 1: ...UG0331 User Guide SmartFusion2 Microcontroller Subsystem ...
Страница 166: ...Cortex M3 Processor Reference Material UG0331 User Guide Revision 15 0 132 ...
Страница 200: ...Embedded NVM eNVM Controllers UG0331 User Guide Revision 15 0 166 Figure 87 System Builder Window ...
Страница 407: ...Universal Serial Bus OTG Controller UG0331 User Guide Revision 15 0 373 ...
Страница 806: ...Fabric Interface Controller UG0331 User Guide Revision 15 0 772 Figure 345 FIC Master AHB Lite Subsystem ...