Universal Serial Bus OTG Controller
UG0331 User Guide Revision 15.0
309
10.3.5
Common Registers
This section covers all registers in this category along with the address offset, functionality, and per bit
details.
Table 198 •
Common Register Set Description
Register Name
Address
Width
R/W
Type
Reset
Value Description
0x40043000 8
RW
0
Write with the 7-bit address of the peripheral part of the
transaction. This register applies to operations when the
USB controller is used in peripheral mode only. It is
ignored in Host mode.
0x40043001 8
R
0x20
Controls suspend and resume signaling and some other
basic operational aspects of the USB controller.
0x40043002 16
R
0
Indicates which interrupts are active for endpoint 0 and
transmit endpoints EP1, EP2, EP3, and EP4. These are
the lowest 5 bits of the register. Interrupts are cleared
when this register is read.
0x40043004 16
R
0
Indicates which interrupts are active for receive
endpoints EP1, EP2, EP3, and EP4. These are bits 1, 2,
3, and 4 of the register. Interrupts are cleared when this
register is read.
0x40043006 16
RW
0x1F
Provides interrupt enables for interrupts in
TX_IRQ_REG. The endpoint0 and EP1, EP2, EP3, and
EP4 have corresponding enable bits from bit 0 to bit 4 of
this register. A value of 1 indicates the interrupt is
enabled.
0x40043008 16
0x1E
Provides interrupt enables for interrupts in
RX_IRQ_REG. The endpoints EP1, EP2, EP3, and EP4
have corresponding enable bits from bit 1 to bit 4 of this
register. A value of 1 indicates the interrupt is enabled.
0x4004300A 8
R
0
Indicates the status of USB interrupts. All active
interrupts are cleared when the register is read.
0x4004300B 8
RW
0x06
Provides interrupt enables for interrupts in
USB_IRQ_REG. A value of 1 indicates the interrupt is
enabled.
0x4004300C 16
R
9
Holds the last received frame number. This is an 11-bit
number.
0x4004300E 4
RW
0
Indicates which endpoint control and status registers are
currently accessed from among the implemented
transmit and receive endpoints (EP0, EP1, EP2, EP3,
and EP4). Each transmit endpoint and each receive
endpoint has its own set of control/status registers
located between 0x40043100 and 0x400431FF
addresses. In addition, one set of TX control/status and
one set of RX control/status registers appear at 10h to
19h. Before accessing an endpoint’s control/status
registers at 10h to 19h, the endpoint number should be
written to the Index register to ensure that the correct
control/status registers appear in the memory map.
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