Serial Peripheral Interface Controller
UG0331 User Guide Revision 15.0
511
The following figure shows the write operation timing for Atmel 25010/020/040 devices. The SPI
controller selects the devices using the slave select signal. The data frame size is set to 24 bits. The SPI
is configured with SPO = 0, SPH = 0. The first byte is the instruction. Bit 5 of the instruction is part of the
address (the 9th bit as required by the Atmel part). Bits 8-15 form a byte address. The residual 8 bits
correspond to the data to be written.
Figure 211 •
Write Operation Timing
Note:
The first byte contains the opcode that defines the operations to be performed. The opcode also contains
address bit A8 in both the READ and WRITE instructions. This is mandated by the Atmel device.
Read Operation for Atmel 25010/020/040 Devices
The following figure shows the read operation timing for Atmel 25010/020/040 devices. For the read
operation, the data frame size is set to 24 bits and the SPI controller is configured with SPO = 0, SPH =
0. On completing, the least significant byte of the received data frame corresponds to the data read.
Figure 212 •
Read Operation Timing
Note:
The first byte contains the opcode that defines the operations to be performed. The opcode also contains
address bit A8 in both the read and write instructions. This is mandated by the Atmel device.
SPI_SS[x]
SPI_CLK
SPI_DO
SPI_DI
Instruction
Byte Address
Data In
9th Bit of Address
High Impedance
0
2
3
4
5
6
7
8
9
10
11
12
13 14
15
16
17
18
20
21
22
23
19
0
2
3
4
5
6
7
8
1
0
2
3
4
5
6
7
1
1
SPI_SS[x]
SPI_CLK
0
2
3
4
5
6
7
8
9
10
11
12
13 14
15
16
17
18
20
21
22
23
19
1
0
2
3
4
5
6
7
8
1
0
2
3
4
5
6
7
1
Data Out
MSB
Byte Address
9th Bit of Address
Instruction
High Impedence
SPI_DI
SPI_DO
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