Serial Peripheral Interface Controller
UG0331 User Guide Revision 15.0
518
For large data transfers, the full depth of transmit FIFO can be used by setting the number of data frames
(more than one) in a burst (maximum is 64 k frames). When the interrupts are enabled, the TXDONE bit
of the
register is asserted after all the data frames in the burst are sent.
For example, if the data frame size is set to 32 and the count is set to 2, the interrupt TXDONE is
generated after every 2 words (each word is 32 bits). The default value for the frame count is one. The
TXUNDERRUN and RXOVERFLOW bits of the
indicate that a FIFO under-run or FIFO
overflow has occurred.
14.2.4.1.1 FIFO Under-Run Condition
If the transmit FIFO is accessed to transfer the data and there is no data in the FIFO, a transmit under-
run error (TXUNDERRUN) is generated. This can be conditionally used to generate an interrupt. In this
case, the transmission is assumed to have been lost and the application must catch the error and restart
the transmission from the beginning. Internally, the transmit logic returns to an idle state and the entire
transmission is deemed lost.
14.2.4.1.2 FIFO Overflow Condition
If the channel attempts to write into a receive FIFO which is already full, a receive overflow error
(RXOVERFLOW) is generated. This can be conditionally used to generate an interrupt. In this case, the
transmission continues but the data is now corrupted because the data frame is missing. It is assumed
that the software clears the interrupt and recover; possibly by reading from the receive FIFO to clear the
source of the interrupt, allowing more data to be received, or even by halting the transmission and
resetting the SPI controller.
14.2.4.2 SPI Controller Modes of Data Transfer
There are two basic modes of transfer.
•
Processor controlled mode: The data transfers are controlled by a firmware that either polls the
register or responds to interrupts.
•
PDMA controlled mode: The data transfers are autonomously controlled by the PDMA engine.
14.2.4.2.1 Processor Controlled Mode
In this mode, the size of the data frames (set in register
) and their numbers (set in the
] field) are specified. The data frame size specifies the number of bits being
shifted out or being received per-frame. On completing each transfer, after a specified number of data
frames (1 by default) are sent, an optional interrupt is generated. The SPI controller keeps track of the
number of data frames so that special signals, like output enable, can be deactivated at the end of a
transfer.
For example, to transmit one 17-bit word, the data frame size is set to 17, and the number of data frames
is set to 1. Then depending on the operating mode, the 17 bits are transferred and the TXDATSENT
register bit (0) is set. If enabled, an interrupt is also generated.
For example, consider the transmission of 64 KB of data to an external EEPROM from the processor
controlled SPI controller. The data frame size is set to eight and the number of data frames per-transfer is
set to one. After each transfer, the software must respond to the interrupt-transmit done-and-reload the
FIFO until the 64 KB of data is sent. To improve throughput, the number of data frames per each transfer
can be set to 4, in order to utilize the full depth of the transmit FIFO.
14.2.4.2.2 PDMA Controlled Mode
In PDMA mode, the interrupts are turned off and the PDMA controller uses SPI_X_TXRFM and
SPI_X_RXAVAIL signals to govern the filling and emptying of the FIFOs. The SPI_X_RXAVAIL signal
indicates that the data is available to be read and SPI_X_TXRFM indicates that the transmit is done and
it is ready to receive more data.
For example, consider the transmission of 64 KB of data to an external EEPROM from a
PDMA controlled SPI controller. The data frame size is set to eight and the number of data frames
per- transfer is set to one. The transmit FIFO is repeatedly filled and emptied by the PDMA engine, using
the SPI_X_TXRFM and SPI_X_RXAVAIL signals. In PDMA mode, the transmit done and receive data
available interrupts are masked, and the PDMA engine is used to notify the application on completion.
Содержание SmartFusion2 MSS
Страница 1: ...UG0331 User Guide SmartFusion2 Microcontroller Subsystem ...
Страница 166: ...Cortex M3 Processor Reference Material UG0331 User Guide Revision 15 0 132 ...
Страница 200: ...Embedded NVM eNVM Controllers UG0331 User Guide Revision 15 0 166 Figure 87 System Builder Window ...
Страница 407: ...Universal Serial Bus OTG Controller UG0331 User Guide Revision 15 0 373 ...
Страница 806: ...Fabric Interface Controller UG0331 User Guide Revision 15 0 772 Figure 345 FIC Master AHB Lite Subsystem ...