Universal Serial Bus OTG Controller
UG0331 User Guide Revision 15.0
346
10.3.10.5 Endpoint4 Control and Status Registers
EP3_TX_INTERVAL_REG 0x013B
8
RW
0
Sets the polling interval for interrupt/ISOC
transactions or the NAK response timeout on
bulk transactions for host transmit endpoint3.
EP3_RX_TYPE_REG
0x013C
8
RW
0
Sets the transaction protocol, speed, and
peripheral endpoint number for the host receive
endpoint3.
EP3_RX_INTERVAL_REG 0x013D
8
RW
0
Sets the polling interval for interrupt/ISOC
transactions or the NAK response timeout on
bulk transactions for host receive endpoint3.
EP3_FIFO_SIZE_REG
0x013E
8
R
Returns the configured size of the endpoint3
receive FIFO and transmit FIFOs.
Table 275 •
Endpoint4 Control and Status Registers
Register Name
Address
Offset from
0x40043000
Width
R/W
Type
Reset
Value Description
EP4_TX_MAX_P_REG
0x0140
16
RW
0
Maximum packet size for host transmit
endpoint4.
EP4_TX_CSR_REG
0x0142
16
R
0
Provides control and status bits for transmit
endpoint4.
EP4_RX_MAX_P_REG
0x0144
16
RW
0
Defines the maximum amount of data that can be
transferred through receive endpoint4 in a single
operation.
EP4_RX_CSR_REG
0x0146
16
R
0
Provides control and status bits for transfers
through the receive endpoint4.
EP4_RX_COUNT_REG
0x0148
16
R
0
Holds the number of data bytes in the packet
currently in line to be read from the endpoint4
receive FIFO. If the packet is transmitted as
multiple bulk packets, the number given will be
for the combined packet.
EP4_TX_TYPE_REG
0x014A
8
W
0
Reads the number of bytes from peripheral
endpoint4 transmit FIFO.
EP4_TX_INTERVAL_REG 0x014B
8
RW
0
Sets the polling interval for interrupt/ISOC
transactions or the NAK response timeout on
bulk transactions for host transmit endpoint4.
EP4_RX_TYPE_REG
0x014C
8
RW
0
Sets the transaction protocol, speed, and
peripheral endpoint number for the host receive
endpoint4.
EP4_RX_INTERVAL_REG 0x014D
8
RW
0
Sets the polling interval for interrupt/ISOC
transactions or the NAK response timeout on
bulk transactions for host receive endpoint4.
EP4_FIFO_SIZE_REG
0x014E
8
R
Returns the configured size of the endpoint4
receive FIFO and transmit FIFOs.
Table 274 •
Endpoint3 Control and Status Registers
(continued)
Register Name
Address
Offset from
0x40043000
Width
R/W
Type
Reset
Value Description
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