Universal Serial Bus OTG Controller
UG0331 User Guide Revision 15.0
325
10.3.6.13 RX_CSRH_REG (in Peripheral mode) Bit Definitions
4
FlushFIFO
0
The Cortex-M3 processor (or fabric master) writes a 1 to this bit to flush the
latest packet from the endpoint receive FIFO. The FIFO pointer is reset and the
RxPktRdy bit (bit 0 of this register) is cleared.
FlushFIFO should only be used when RxPktRdy is set. At other times, it may
cause data to be corrupted.
If the FIFO is double-buffered, FlushFIFO may need to be set twice to completely
clear the FIFO.
3
DataError
0
When operating in ISO mode, this bit is set when RxPktRdy (bit 0 of this register)
is set, if the data packet has a CRC or bit-stuff error, and cleared when RxPktRdy
is cleared. In Bulk mode, this bit is set when the receive endpoint is halted,
following the receipt of NAK responses for longer than the time set as the NAK
limit by the RxInterval register. The Cortex-M3 processor (or fabric master)
should clear this bit to allow the endpoint to continue. However, if double packet
buffering is enabled, this alone will not allow the transfer to continue. In this case,
the reqpkt bit should also be set in the same cycle this bit is cleared.
NAK Timeout 0
2
Error
0
The USB controller sets this bit when 3 attempts have been made to receive a
packet and no data packet has been received. The Cortex-M3 processor (or
fabric master) should clear this bit.
This bit is only valid when the Rx endpoint is operating in Bulk or Interrupt mode.
In ISO mode, it always returns zero.
1
FIFOFull
0
This bit is set when no more packets can be loaded into the receive FIFO.
0
RxPktRdy
0
This bit is set when a data packet has been received. The Cortex-M3 processor
(or fabric master) should clear this bit when the packet has been unloaded from
the receive FIFO. An interrupt is generated when the bit is set.
Table 224 •
RX_CSRH_REG (Peripheral)
Bit
Number
Name
Reset
Value
Function
7
AutoClear
0
If the Cortex-M3 processor (or fabric master) sets this bit then the RxPktRdy bit
(bit 0 in RXCSRL_REG) will be automatically cleared when a packet of
RxMaxP (RX_MAX_P_REG) bytes has been unloaded from the receive FIFO.
When packets of less than the maximum packet size are unloaded, RxPktRdy
will have to be cleared manually. When using a DMA to unload the receive
FIFO, data is read from the receive FIFO in 4-byte chunks, regardless of the
RxMaxP. Therefore, the RxPktRdy bit will be cleared, as shown in
page 326.
Should not be set for high-bandwidth ISO endpoints.
6
ISO
0
The Cortex-M3 processor (or fabric master) sets this bit to enable the receive
endpoint for ISO transfers, and clears it to enable the receive endpoint for
bulk/interrupt transfers.
5
DMAReqEnab
0
The Cortex-M3 processor (or fabric master) sets this bit to enable the DMA
request for the receive endpoint.
Table 223 •
RX_CSRL_REG (Host)
(continued)
Bit
Number
Name
Reset
Value
Function
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