Cortex-M3 Processor Overview and Debug Features
UG0331 User Guide Revision 15.0
15
2.5.2.1
Data Watch Point (DWP) and Trace
The DWT unit is able to provide either focused data trace or global data trace. It has four comparators
used to compare the following conditions:
•
Hardware watch point: generates a watch point event to the processor to invoke debug modes such
as halt or debug monitor.
•
ETM trigger: causes the ETM to emit a trigger packet in the instruction trace stream.
•
PC sampler event trigger
•
Data address sample trigger
2.5.2.2
Instrumentation Trace Macrocell
ITM provides the support for the debug message output, such as printf, and feeds output to the TPIU.
ITM uses a FIFO to buffer the output messages and outputs are not delayed as UART transfers. The
output messages can be collected at the TPI or the SWV interface on TPIU. ITM timestamps the outputs
and it outputs the messages from the DWT unit.
2.5.2.3
Embedded Trace Macrocell
The ETM block is a high speed, low power-consumption debugging tool that provides instruction trace
only, and which feeds output to the TPIU. The ETM has a FIFO queue of 24 bytes, and ETM outputs 8
bits of data at a time at the core clock speed. This output is compatible with the AMBA trace bus (ATB).
The ETM trace is supported by tools like Keil Trace, IAR Trace, Greenhills software trace, and others.
The ETM provides the following features:
•
Tracing of 16-bit and 32-bit thumb instructions
•
Four EmbeddedICE watchpoint inputs
•
A Trace Start/Stop block with EmbeddedICE inputs
•
Two external inputs
•
Global time-stamping
2.6
Cortex-M3 Processor Port Descriptions
The following table lists all the ports related to the Cortex-M3 subsystem, their direction, and a
description of the ports.
JTAG_TDO/
M3_TDO/
M3_SWO
TDO
SWO
SWO
JTAG_TDI/
M3_TDI
TDI
TRACECLK
TRACEDATA[3:0]
Table 4 •
Port Details of the Cortex-M3-Subsystem
Port Name
Direction
Pad
Description
RXEV
In
No
Causes the Cortex-M3 to wake up from a wait for event (WFE) instruction.
The event input, RXEV, is registered even when not waiting for an event,
and so affects the next WFE.
TXEV
Out
No
Event transmitted as a result of a Cortex-M3 SEV (send event) instruction.
This is a single-cycle pulse equal to 1 M3_CLK period.
SLEEP
Out
No
Signal is asserted when the Cortex-M3 processor is in sleep now or sleep-
on-exit mode, and indicates that the clock to the processor can be stopped.
Table 3 •
Signal Multiplexing
(continued)
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