AHB Bus Matrix
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high priority master is requesting access to the slave. Only after completing 8 transfers, the high priority
master will gain access to the slave.
The following table gives an arbitration scenario for a non-eSRAM slave. In this scenario, master M5
(FIC_1) starts a burst of twelve transfers (reads typically for accesses to eNVM) to slave S2 (eNVM_0) in
the first clock cycle. In the second clock, fixed priority master M1 (DCode bus) bus tries to access the
same slave. Since the programmed weight of M5 master is 8, the M1 master does not gain access to the
slave until M5 completes eight transfers. As seen in the table,
the M1 master gains access to the slave
only after the M5 master completes eight transfers, which is in the 9th clock cycle. The M5 master has to
re-arbitrate for the slave to complete the remaining transfers. So the maximum latency seen by the
Cortex-M3 processor bus M1 is equal to the programmed weight of 8.
7.1.3.1.4
Arbitration for eSRAM Slaves
For eSRAM slaves, the maximum latency seen by Cortex-M3 processor bus masters can affect overall
system performance. To manage this latency, a programmable maximum latency parameter
SW_MAX_LAT_ESRAM<0/1> is available to optimize arbitration for the eSRAM slaves from a fixed
priority master. The parameter SW_MAX_LAT_ESRAM_<0/1> sets a ceiling as to the number of cycles
the Cortex-M3 processor bus master, or any fixed priority master, has to wait before accessing an
eSRAM slave that is currently being accessed by a WRR master. When a WRR master has a
programmable weight greater than the SW_MAX_LAT_ESRAM<0/1> value, the WRR master will have to
re-arbitrate for the slave after SW_MAX_LAT_ESRAM<0/1> cycles. The following equation gives the
maximum latency seen by a processor master while accessing an eSRAM slave:
Maximum latency seen by the Cortex-M3 processor master = min {programmable weight (WRR master),
SW_MAX_LAT_ESRAM<0/1>}
For example, if SW_WEIGHT_HPDMA is set to 18 and SW_MAX_LAT_ESRAM0 is set to 4, then the
maximum latency is min {18, 4} = 4. Similarly, if SW_WEIGHT_PDMA is set to 2 and
SW_MAX_LAT_ESRAM1 is set to 6, then the maximum latency is min {2, 6} = 2. The following table
depicts a typical scenario.
In this scenario, the slave maximum latency is set to 4 and the master programmable weight is set to 8,
so the maximum latency seen by the processor bus master is min {4, 8} = 4. When the WRR master
starts transactions with the eSRAM slave, it can perform a number of transactions equal to the
programmed maximum latency or the programmed weight, whichever is less, before re-arbitrating for the
slave.
Table 143 •
WRR and Fixed Priority Arbitration Scenario for eNVM_0
Master
HCLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
M3-D: M1
S2-
B4
FIC_1: M5 S2-
B12
eNVM_0:S
2
M5-
B1
M5-
B2
M5-
B3
M5-
B4
M5-
B5
M5-
B6
M5-
B7
M5-
B8
M1-
B1
M1-
B2
M1-
B3
M1-
B4
M5-
B9
M5-
B10
M5-
B11
M5-
B12
Table 144 •
WRR Arbitration Scenario for eSRAM_0 slave
Master
HCLK
1
2
3
4
5
6
7
8
9
10
11
12
M3-D: M1
S0-B4
PDMA: M7
S0-B8
eSRAM_0: S0 M7-B1 M7-B2 M7-B3 M7-B4 M1-B1 M1-B2 M1-B3 M1-B4 M7-B5 M7-B6 M7-B7 M7-B8
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