High Performance DMA Controller
UG0331 User Guide Revision 15.0
252
8.4.1.6
Descriptor 0 Destination Address Register
8.4.1.7
Descriptor 1 Destination Address Register
8.4.1.8
Descriptor 2 Destination Address Register
8.4.1.9
Descriptor 3 Destination Address Register
8.4.1.9.1
Notes on the Destination Address Register (DAR)
•
Address is word aligned at the start.
•
Address increments on each successful transfer at the destination end.
•
HPDMA controller starts reading the data from source memory and transfers to destination memory.
•
Software can write all 32-bit destination addresses to prevent non-word aligned transfers at the start
and 2 LSBs, 1:0, are masked in the hardware.
•
The destination address will be updated in the same field when the descriptor transfer is in progress.
Table 155 •
HPDMAD0DAR_REG
Bit Number Name
Reset Value Description
31:0
HPDMADAR_DCP0_DST_ADRS 0x00
Descriptor 0 destination end memory start address
Table 156 •
HPDMAD1DAR_REG
Bit Number Name
Reset Value Description
31:0
HPDMADAR_DCP1_DST_ADRS 0x00
Descriptor 1 destination end memory start address
Table 157 •
HPDMAD2DAR_REG
Bit Number Name
Reset Value Description
31:0
HPDMADAR_DCP2_DST_ADRS
0x00
Descriptor 2 destination end memory start address
Table 158 •
HPDMAD3DAR_REG
Bit Number Name
Reset Value Description
31:0
HPDMADAR_DCP3_DST_ADRS
0x00
Descriptor 3 destination end memory start address
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