Embedded SRAM (eSRAM) Controllers
UG0331 User Guide Revision 15.0
204
Note:
page 210 for more information on AHB Bus Matrix masters and slaves.
Table 133 •
MM3_6_7_8_SECURITY
Bit
Number Name
Reset
Value
Description
[31:10]
Reserved
0
Reserved
9
MM3_6_7_8_MS6_ALLOWED_W
1
Write security bits for masters 3, 6, 7, and 8 to slave 6 (MSS
DDR bridge). If not set, masters 3, 6, 7, and 8 will not have
write access to slave 6.
8
MM3_6_7_8_MS6_ALLOWED_R
1
Read security bits for masters 3, 6, 7, and 8 to slave 6 (MSS
DDR bridge). If not set, masters 3, 6, 7, and 8 will not have
read access to slave 6.
7
MM3_6_7_8_MS3_ALLOWED_W
1
Write security bits for masters 3, 6, 7, and 8 to slave 3
(eNVM1). If not set, masters 3, 6, 7, and 8 will not have write
access to slave 3.
6
MM3_6_7_8_MS3_ALLOWED_R
1
Read security bits for masters 3, 6, 7, and 8 to slave 3
(eNVM1). If not set, masters 3, 6, 7, and 8 will not have read
access to slave 3.
5
MM3_6_7_8_MS2_ALLOWED_W
1
Write security bits for masters 3, 6, 7, and 8 to slave 2
(eNVM0). If not set, masters 3, 6, 7, and 8 will not have write
access to slave 2.
4
MM3_6_7_8_MS2_ALLOWED_R
1
Read security bits for masters 3, 6, 7, and 8 to slave 2
(eNVM0). If not set, masters 3, 6, 7, and 8 will not have read
access to slave 2.
3
MM3_6_7_8_MS1_ALLOWED_W
1
Write security bits for masters 3, 6, 7, and 8 to slave 1
(eSRAM1). If not set, masters 3, 6, 7, and 8 will not have
write access to slave 1.
2
MM3_6_7_8_MS1_ALLOWED_R
1
Read security bits for masters 3, 6, 7, and 8 to slave 1
(eSRAM1). If not set, masters 3, 6, 7, and 8 will not have
read access to slave 1.
1
MM3_6_7_8_MS0_ALLOWED_W
1
Write security bits for masters 3, 6, 7, and 8 to slave 0
(eSRAM0). If not set, masters 3, 6, 7, and 8 will not have
write access to slave 0.
0
MM3_6_7_8_MS0_ALLOWED_R
1
Read security bits for masters 3, 6, 7, and 8 to slave 0
(eSRAM0). If not set, masters 3, 6, 7, and 8 will not have
read access to slave 0.
Table 134 •
MM9_SECURITY
Bit
Number Name
Reset
Value
Description
[31:10]
Reserved
0
Reserved
9
MM9_MS6_ALLOWED_W
1
Write security bits for master 9 to slave 6 (MSS DDR bridge). If
not set, master 9 will not have write access to slave 6.
8
MM9_MS6_ALLOWED_R
1
Read security bits for master 9 to slave 6 (MSS DDR bridge). If
not set, master 9 will not have read access to slave 6.
Содержание SmartFusion2 MSS
Страница 1: ...UG0331 User Guide SmartFusion2 Microcontroller Subsystem ...
Страница 166: ...Cortex M3 Processor Reference Material UG0331 User Guide Revision 15 0 132 ...
Страница 200: ...Embedded NVM eNVM Controllers UG0331 User Guide Revision 15 0 166 Figure 87 System Builder Window ...
Страница 407: ...Universal Serial Bus OTG Controller UG0331 User Guide Revision 15 0 373 ...
Страница 806: ...Fabric Interface Controller UG0331 User Guide Revision 15 0 772 Figure 345 FIC Master AHB Lite Subsystem ...