Reset Controller
UG0331 User Guide Revision 15.0
643
21.1
Functional Description
21.1.1
Power-On Reset Generation Sequence
The following figure shows the conceptual block diagram of power-on reset generation. The POR
generator block in System Controller generates a power-on reset signal, PO_RESET_N.
Figure 276 •
Conceptual Block Diagram of Power-On Reset Generation
page 645 shows the power up to functional time sequence diagram. On power-up, the VDD
and VPP monitor blocks in the POR generator block assert a power-on reset signal, PO_RESET_N. If
the VDD and VPP supplies reach their threshold point (VDD ~ 0.9 V, VPP ~0.9 V), the 1 MHz RC
Oscillator is turned-on, which provides the clock to the programmable delay counter. The delay can be
configured to 50 µs, 1 ms, 10 ms, or 100 ms in the New Project window (Device Settings) while creating
the Libero SoC project as shown in the following figure. You can also access and change this setting
after the project has been created from the Project Settings window (Project > Project Settings…). The
delay setting (Power on Reset Delay) get implemented in the design while generating bitstream.
MSS
SC
Reset Controller
PO_RESET_N
System Controller
1 MHz
RC Oscillator
SmartFusion2 SoC FPGA
Reset Controller
VDD and VPP
Monitor
Programmable
Delay Counter
POR
Generator
PO_RESET_N
FPGA Fabric
DEVRST_N
POWER_ON_RESET_N
MSS_RESET_N_M2F
Содержание SmartFusion2 MSS
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