Document #: GP-UM-PMD-1000-21
Page 38 of 122
Figure 22 Effect of input polarization alignment on PMD effect caused by a DGD element
a) Equal power split between fast and slow axes
b) Input polarization aligned to fast axis- pulse is not distorted
c) Input polarization aligned to slow axis- pulse is phase delayed but not distorted
In the second case, the output polarimeter reading is used to control the polarization
controller to tune the input polarization state to minimize the DOP of the signal after it
passes through the PMD element.
When WSOP is selected, the screen displays 2 options:
1.
EQUAL POWER SPLIT:
This option can be used with a DGD-only (SOPMD = 0) discrete mode state
(PMD ID#0-255). It aligns the polarization state of the signal at the input to the
PMD element such that the power is split equally between polarization
components aligned to the slow and fast axes of the PMD element.
If the PMD setting is a continuous mode state or a lookup table state with an ID#
>255, the following error message will be displayed when the equal power split
option is selected:
*Active in DGD only*
Discrete: ID# 0 to 255
1. EQUAL POWER SPLIT
2. OUTPUT DOP TO MIN
