3 . I n s t r u c t i o n S e t
M N 0 5 0 0 3 0 0 3 E F o r m o r e i n f o r m a t i o n v i s i t :
w w w. e a t o n . c o m
3 - 2 9 1
API Mnemonic
Operands
Function
107
LRC P
S, n, D
LRC Generator
Bit Devices
Word devices
Program Steps
Type
OP
X Y M S K H KnX KnY KnM KnS T
C
D
E
F
S
*
n
*
*
*
D
*
LRC, LRCP: 7 steps
ELC ELCB
ELCM
PB PC/PA/PH
PV
PB PH/PA
32
16
P
32
16
P
32
16
P
32 16
P
32
16
P
Operands:
S
: Starting address for the checksum operation (ASCII mode)
n
: Number of values to perform the
operation on (
n
=K1~K256)
D
: Destination for storing the operation result
Description:
1.
n
:
n
must be even. If
n
is out of range, an error will occur and the instruction will not be
executed. If an error occurs, M1067 and M1068 = ON and error code H’0E1A will be recorded
in D1067.
2.
16-bit conversion mode: When M1161= OFF, hexadecimal data that starts from the source
S
will be divided into upper 8-bit and lower 8-bit values and the checksum operation will be
performed on
n
values. Then, the result will be stored in the upper and lower 8-bits of
D
.
3.
8-bit conversion mode: When M1161= ON, divide the hexadecimal data that starts with source
address
S
into upper 8-bit (invalid data) and lower 8-bit and perform the checksum operation
on
n
values. Then, store the result in the lower 8-bits of
D
(upper 8-bits of
D
will be zero (0)).
4.
Flag: M1161 8/16-bit mode
Program Example:
ASCII
communication mode: Data stored as following:
Register
Data
Descriptions
D100 low byte
‘: ’
3A H
STX
D101 low byte
‘0’
30 H
ADR 1
D102 low byte
‘1’
31 H
ADR 0
ADR (1,0) is AC drive address
D103 low byte
‘0’
30 H
CMD 1
D104 low byte
‘3’
33 H
CMD 0
CMD (1,0) is instruction code
D105 low byte
‘0’
30 H
D106 low byte
‘7’
37 H
D107 low byte
‘0’
30 H
D108 low byte
‘8’
38 H
Starting data address
D109 low byte
‘0’
30 H
D110 low byte
‘0’
30 H
Number of data (count by word)
Содержание ELC-PB
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