Interrupt Controller (8259A)
Read/Write Control Logic
The Read/Write Control Logic controls command and data transfer
between the PIC and the CPU. This functional block selects a PIC
register and determines the direction of data travel based on the
address and I/O control inputs.
Initialization and Operation Registers
Several registers in the PIC store programmed information regarding
the handling of interrupts. The initialization registers store the four
Initialization Control Words (ICWs), which must be written to the
PIC in the order of ICW1 through ICW4 before CPU interrupts are
enabled. Once initialized, the operation of the PIC is controlled by the
Operation Control Words (OCWs). The OCWs control the interrupts
to be masked, the End-of-Interrupt (EOI) indication, interrupt priority
rotation, and the reading of certain PIC registers. ICW1 through
ICW4 are described more fully beginning on page 12-12. Description
of the OCWs begins on page 12-16.
Cascade Buffer/Comparator
The 8259A Programmable Interrupt Controller can be cascaded with
other 8259A PICs to increase the number of interrupt inputs from 8
up to 43. Briefly, cascading involves connecting the interrupt output
from external 8259A PICs in the STD system to interrupt inputs on
the
ZT 8809A
PIC.
Each
of
these
external "slave"
PICs
communicates to the ZT 8809A "master" PIC via a 3-bit cascade
address. This cascade address is driven by the master and indicates
which slave (if any) should provide the vector address for the proper
interrupt service routine. These cascade address bits are driven over
the STD bus backplane signals A8-10 during interrupt acknowledge
time. The cascade buffer/comparator logic inside each 8259A is used
to cascade interrupt controllers in this manner.
12-10
