Serial Communications (16C452)
Line Status Register
(2FDh, 3FDh; R/W)
This 8-bit register provides status information to the CPU concerning
the data transfer. Reading the Line Status register (LSR) clears bits 1
through 4 (OE, PE, FE, and BI). The contents of the LSR are
included in Table 8-3 on pages 8-18 and 8-19, and a description
follows.
Bit 0
This bit is the receiver Data Ready (DR) indicator.
Bit 0 is set to logical 1 whenever a complete
incoming character has been received and transferred
into the Receiver Buffer register. Bit 0 may be reset
to logical 0 either by the CPU reading the data in the
Receiver Buffer register or by writing a logical 0 into
the LSR from the CPU.
Bit 1
This bit is the Overrun Error (OE) indicator.
It
indicates that data in the Receiver Buffer register was
not read by the CPU before the next character was
transferred into the Receiver Buffer register, thereby
destroying the previous character. The OE indicator
is reset whenever the CPU reads the contents of the
LSR.
Bit 2
This bit is the Parity Error (PE) indicator. Bit 2
indicates that the received data character does not
have the correct even or odd parity, as selected by the
Even Parity Select bit. The PE bit is set to logical 1
upon detection of a parity error and is reset to
logical 0 whenever the CPU reads the contents of the
LSR.
Bit 3
This bit is the Framing Error (FE) indicator. Bit 3
indicates that the received character did not have a
valid stop bit. Bit 3 is set to logical 1 whenever the
stop bit following the last data bit or parity bit is
detected as a zero bit (spacing level).
8-26
