Serial Communications (16C452)
Modem Status Register
(2FEh, 3FEh; R)
The Modem Status register (MSR) provides the current state of the
control lines from the modem (or peripheral device) to the CPU. In
addition to this current-state information, four bits of the MSR
provide change information.
These bits are set to logical 1 whenever a control input from the
modem changes state. They are reset to logical 0 whenever the CPU
reads the MSR. The contents of the MSR are included in Table 8-3 on
pages 8-18 and 8-19 and are described below.
Bit 0
This bit is the Delta Clear-To-Send (DCTS) indicator.
Bit 0 indicates that the CTS input to the chip has
changed state since the last time it was read by the
CPU.
Bit 1
This bit is the Delta Data-Set-Ready (DDSR)
indicator. Bit 1 indicates that the DSR input to the
chip has changed state since the last time it was read
by the CPU.
Bit 2
This bit is the Trailing Edge-of-Ring Indicator
(TERI) detector. Bit 2 indicates the RI* input to the
chip has changed from an On (logical 1) to an Off
(logical 0) since the last time it was read by the CPU.
Bit 3
This bit is the Delta Received Line Signal Detector
(DRLSD) indicator. Bit 3 indicates that the RLSD
input to the chip has changed state since the last time
it was read by the CPU.
Bit 4
This bit is the complement of the Clear-To-Send
(CTS*) input. When set, it indicates that the modem
is ready to receive data from the Serial Channels
Transmitter Output (SOUT). If bit 4 of the MCR is
set (loopback mode), this bit is equivalent to RTS* in
the MCR.
8-33
