Interrupt Controller (8259A)
Level-Triggered Mode
When in the level-triggered mode, the 8259A recognizes any active
(high) level on an IR input as an interrupt request. If the IR input
remains active after an EOI command has been issued (resetting its
ISR bit), another interrupt is generated. This occurs if the processor
INT pin is enabled. Unless repetitious interrupt generation is desired,
the IR input must be brought to an inactive state before an EOI
command is issued in its service routine.
Note that the request on the IR input must remain until after the
falling edge of the first INTA* pulse. If on any IR input the request
goes inactive before the first INTA* pulse, the 8259A responds as if
IR7 were active. In any design in which this may occur, the IR7
default feature can be used as a safeguard. You may accomplish this
by using the IR7 routine as a "clean-up routine" that might recheck
the 8259A status or merely return program execution to its pre-
interrupt location.
Depending upon the particular design and application, the level-
triggered mode for the operation is selected by the EOI, SL, and R
bits of OCW2. The level-triggered mode has a number of uses. For
example, it provides for repetitious interrupt generation. This is useful
if a service routine needs to be continually executed until the interrupt
request goes inactive.
Note: Caution should be taken when using the automatic EOI mode
and the level-triggered mode together. In the automatic EOI mode, an
EOI is automatically performed at the end of the interrupt
acknowledge sequence. If the processor enables interrupts while an IR
input is still high, an interrupt will occur immediately. To avoid this,
interrupts should be kept disabled until the end of the service routine
or until the IR input returns low.
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